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EP0174397A2
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Dummy load controlled multi-level logic single clock logic circuit
Assignee: Texas Instruments Inc
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Filing: 1984-08-03
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Granted: —
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Expires: 2004-08-03
Abstract
Abstract A multi-level logic circuit includes a first plurality of logic circuits that are connected in a cascade arrangement. A second plurality of dummy logic circuits also connected in casacade arrangement are used to generate logic pulses for evaluating the first plurality of logic circuits. A clock source provides a precharged signal to the first plurality of logic circuits and the second plurality of dummy logic circuits and an evaluation circuit is used to combine the clock signal with an output signal from the dummy logic signal to obtain an evaluation signal for evaluating the logic states of the first plurality of logic circuits. A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier. Each operation set is applied to a second plurality of n partial products selectors which are connected in cascade arrangement according to multiplicand sets and wherein each partial product selector multiplicand set implements one of the recoded Booth operation sets. The outputs of the partial product selectors are summed by a summation means and a domino circuit means provides an evaluation pulse for each member of the partial product selector at the completion of the Booth operation set that is connected to the partial product selector.
Inventors
- 👤 Graham S. Tubbs
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 06:26
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3872; G06F2207/3884
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
101 words
An multi-level logic circuit comprising: a first plurality of N logic circuit means, connected in cascade arrangement where N is a positive integer, for performaning logic operation; a second plurality of N dummy logic circuit means, connected in cascade arrangement where M is a positive integer, for providing a plurality of M evaluation pulses; clock circuit means for providing a precharge signal to each member of the plurality logic circuit means and the dummy logic circuit means; and circuit means for evaluating each member of the plurality of logic circuit means with a corresponding member of the plurality of evaluation pulses.
Claim 2
Dependent Claim
101 words
An multi-level logic circuit comprising: a first plurality of N logic circuit means, connected in cascade arrangement where N is a positive integer, for performaning logic operation; a second plurality of N dummy logic circuit means, connected in cascade arrangement where M is a positive integer, for providing a plurality of M evaluation pulses; clock circuit means for providing a precharge signal to each member of the plurality logic circuit means and the dummy logic circuit means; and circuit means for evaluating each member of the plurality of logic circuit means with a corresponding member of the plurality of evaluation pulses.
Claim 3
Dependent Claim
13 words
The multi-level logic circuit according to Claim 1 comprises: a programmmable logic array.
Claim 4
Dependent Claim
73 words
The multi-level logic-circuit according to Claim 2 wherein the programmable logic array comprises: an x by y matrix logic means where x and y are both positive integers representing the data input line and the number of decode lines respectively; and (Claim 3 continued) the dummy logic means include a single logic array means connected in a worst case condition to provide an enable pulse to the x by y matrix logic means.
Claim 5
Dependent Claim
55 words
The multi-level logic circuit according to Claim 3 wherein the programmable logic array further comprises: an output stage means for providing output signals representative of the program decoded by the signal and the data input lines the program stored in the x by y matrix, said output stage means being enabled by the enable signal.
Claim 6
Dependent Claim
46 words
The multi-level logic circuit according to Claim 1 wherein circuit means comprises: AND gate means for combining the precharge signal with the evaluation signal such that when the precharge signal is not present and the evaluation signal is present, a corresponding logic circuit means is evaluated.
Claim 7
Dependent Claim
105 words
A method of implementing a multi-level logic circuit comprising: connecting a first plurality of logic circuit means in cascade arrangements wherein the plurality of logic circuit means are for performing logic operations; connecting a second plurality dummy logic circuit means in cascade arrangement wherein the dummy logic circuit means provide a plurality of evaluation pluses from the second plurality of dummy logic circuits; (Claim 6 continued) providing a precharge signal to each member of the plurality logic circuit means and the dummy logic circuit means; and evaluating each member of the plurality logic circuit means with the corresponding member of a plurality of evaluation pulses.
Claim 8
Dependent Claim
63 words
A programmable logic array comprising: a x by y matrix logic means where x and y are both positive integers representing a data input line and the number of decode lines respectively; and a dummy logic means that includes a single logic array means connected in a worse case arrangement to provide and evaluation pulse to the x and y matrix logic means.
Claim 9
Dependent Claim
63 words
A programmable logic array comprising: a x by y matrix logic means where x and y are both positive integers representing a data input line and the number of decode lines respectively; and a dummy logic means that includes a single logic array means connected in a worse case arrangement to provide and evaluation pulse to the x and y matrix logic means.
Claim 10
Dependent Claim
45 words
8 . The programmable logic array according to Claim 7 further comprising an output stage means for providing an output signal representative of the program decoded by the signal on the data input links and the program stored in the x by y matrix means.
Claim 11
Dependent Claim
162 words
A digital multiplication circuit comprising: a Booth recoder means for recoding a multiplier into N Booth operation sets where N is a positive integer that equals one half the number of bits in the multiplier; a plurality of N partial product selector means connected in cascade arrangement of multiplicand sets of M length and each member of the plurality of N partial product selector means being connected to a member of the M operation sets for implementing the recoded Booth operation set on a multiplicand set and where M is a positive integer; summation means for summing the contents of the plurality of N partial product selector means the summation means being located between members of the plurality of N partial product selector means; and a domino means including summation circuit means for generating a next evaluation pulse to evaluate a corresponding member of the plurality of partial product selector means whose input circuits are connected to a corresponding summation means output.
Claim 12
Dependent Claim
162 words
A digital multiplication circuit comprising: a Booth recoder means for recoding a multiplier into N Booth operation sets where N is a positive integer that equals one half the number of bits in the multiplier; a plurality of N partial product selector means connected in cascade arrangement of multiplicand sets of M length and each member of the plurality of N partial product selector means being connected to a member of the M operation sets for implementing the recoded Booth operation set on a multiplicand set and where M is a positive integer; summation means for summing the contents of the plurality of N partial product selector means the summation means being located between members of the plurality of N partial product selector means; and a domino means including summation circuit means for generating a next evaluation pulse to evaluate a corresponding member of the plurality of partial product selector means whose input circuits are connected to a corresponding summation means output.
Claim 13
Dependent Claim
41 words
The digital multiplication circuit according .to Claim 9 wherein the domino circuit means comprises: a clock means for providing a precharge signal; and a partial product stage means connected in cascade arrangement for converting the precharge signal to an evaluative signal.
Claim 14
Dependent Claim
68 words
The digital multiplication circuit according to Claim 10 wherein the domino circuit means futher comprises: a plurality of dummy load means; and a plurality of summation circuits connected to a pre-selected dummy load means for providing an evaluation pulse to each member of plurality of P1 partial product selector means at the completion of the Booth operation set that is connected to the corresponding partial product selector means.
Claim 15
Dependent Claim
32 words
The digital multiplication circuit according to Claim 9 wherein the summation means comprises; a plurality of full adder circuit means for combining a first input, a second input, and a third input.
Claim 16
Dependent Claim
35 words
The digital multiplication circuit according to Claim L1 wherein each of the plurality of the summation circuit means comprises: a full adder circuit means having a first input a second input, and a third input.
Claim 17
Dependent Claim
62 words
The digital multiplication circuit according to Claim 9 wherein the summation means comprises: a first plurality of full adder circuits connected to sum the output of a first multiplicand set from a preselected partial product selector means, a second multiplicand. set from a second preselected partial product selector means and a third multiplicand set of a third preselected partial product selector means.
Claim 18
Dependent Claim
50 words
The digital multiplication circuit according to Claim 14 wherein the summation means further comprising: a second set of full adder circuit means for combining the output of the first set of full adder means with the output of a fourth multiplicand set of a fourth preselected partial product selector means.
Claim 19
Dependent Claim
48 words
The digital multiplication circuit according to Claim 10 wherein the summation means further comprises: a third set of full adder circuit means connected to combine the output of the second sent of full adder means with a fifth multiplicand set of a fifth preselected partial product selector means.
Claim 20
Dependent Claim
47 words
The digital multiplication circuit according to Claim .6 wherein the summation means further comprises: a fourth set of full adder means for combining the output of this third set of the full adder means with a sixth multiplicand set of a sixth preselected partial product selector means.
Claim 21
Dependent Claim
31 words
The digital multiplication circuit according to Claim 9 further comprising; an intermediate set of registers for storing the outputs of the plurality of the partial product selectors and the summation means.
Claim 22
Dependent Claim
35 words
The digital multiplication circuit according to Claim 18 further comprising; a second summation circuit means for selectively combining the outputs of the intermediate register means to obtain the product of the multiplicand and the multiplier.
Claim 23
Dependent Claim
27 words
The digital multiplication circuit means according to Claim 19 further comprising: a plurality of storage register means for storing the products of the multiplier and the multiplicand
Claim 24
Independent Claim
133 words
A method of performing digital multiplication comprising: decoding a multiplier into N Booth operation sets where N is a positive integer that equals one half the number of bits in the multiplier; implementing a decoded Booth operation set on a multiplicand with a plurality of N partial product selector means connected in cascade arrangement and each member of the plurality of N partial product selector means being connected to receive a member of the N operation sets; summing the contents of the plurality of N partial product selector means with a summation means located between members of the plurality of N partial product registers; and generating a next evaluation pulse to evaluate the member of the plurality of partial product selector means whose input circuits are connected to a corresponding summation means output.
Claim 25
Independent Claim
133 words
A method of performing digital multiplication comprising: decoding a multiplier into N Booth operation sets where N is a positive integer that equals one half the number of bits in the multiplier; implementing a decoded Booth operation set on a multiplicand with a plurality of N partial product selector means connected in cascade arrangement and each member of the plurality of N partial product selector means being connected to receive a member of the N operation sets; summing the contents of the plurality of N partial product selector means with a summation means located between members of the plurality of N partial product registers; and generating a next evaluation pulse to evaluate the member of the plurality of partial product selector means whose input circuits are connected to a corresponding summation means output.
Claim 26
Dependent Claim
29 words
The method according to Claim 19 wherein the step of generating a next evaluation pulse comprises: providing a precharge signal; and converting the precharge signal to an evaluative signal.
References Cited (Backward Citations)
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