Patent EP0173980A2 successfully refreshed from Google Patents.
EP0173980A2
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EP
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Semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1985-08-30
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Granted: —
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Expires: 2005-08-30
Abstract
Abstract In an MOS integrated circuit device, the level of the back-bias voltage (-Vbb) which is generated by a built-in back-bias generation circuit (Vbb-G) and is supplied to a semiconductor substrate is changed by undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant but becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, the back-bias voltage generation circuit (Vbb-G) has an output capacity of a plurality of levels. The output capacity is increased in response to an operation control signal of the main circuit. The level change of the back-bias voltage generation circuit (Vbb-G) can further be reduced by providing a level detection circuit (VLD) for detecting the level change and a feedback circuit for controlling the back-bias voltage generation circuit in accordance with the output of the level detection circuit (VLD)
Inventors
- 👤 Katsuyuki Sato
- 👤 Kazumasa Yanagisawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 18:34
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C5/146; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
87 words
A semiconductor integrated circuit device comprising: a first circuit which includes insulated gate field effect transistors (Qm) having a substrate gate to which a back-bias voltage (-Vbb) is supplied, and whose operation is controlled by a control signal (RAS1); and a back-bias voltage generation circuit (Vbb-G) for generating said back-bias voltage (-Vbb), having the operation thereof controlled on the basis of said control signal (RAS1) in such a fashion that the voltage output capacity thereof is changed in synchronism with the operating state of said first circuit.
Claim 2
Dependent Claim
87 words
A semiconductor integrated circuit device comprising: a first circuit which includes insulated gate field effect transistors (Qm) having a substrate gate to which a back-bias voltage (-Vbb) is supplied, and whose operation is controlled by a control signal (RAS1); and a back-bias voltage generation circuit (Vbb-G) for generating said back-bias voltage (-Vbb), having the operation thereof controlled on the basis of said control signal (RAS1) in such a fashion that the voltage output capacity thereof is changed in synchronism with the operating state of said first circuit.
Claim 3
Dependent Claim
73 words
The device of claim 1 wherein said back-bias voltage generation circuit (Vbb-G) comprises a first rectification circuit including a capacitor (C2) and a plurality of rectification elements (Q20, Q21) and receiving periodic pulse signals, a second rectification circuit including a capacitor (C1) and a plurality of rectification elements (Q18, Q19), and a control circuit (G1) for controlling pulse signals supplied to said second rectification circuit on the basis of said control signal (RAS1).
Claim 4
Dependent Claim
55 words
The device of claim 2 wherein said pulse signal to be supplied to said second rectification circuit is set to a level such that said capacitor (C1) of said second rectification circuit is brought into a pre-charge state when said control signal (RAS1) is at such a level as to render said first circuit inoperative.
Claim 5
Dependent Claim
70 words
The device of claim 2 or 3 wherein said back-bias voltage generation circuit lVbb-G) comprises a first oscillation circuit (OSC2) for generating pulse signals to be supplied to said first rectification circuit and a second oscillation circuit ( OSC1 ) having the operation thereof controlled in response to an operation control signal produced from said control circuit (G1), and generating pulse signals to be supplied to said second rectification circuit.
Claim 6
Dependent Claim
27 words
The device of claim 4 wherein said second oscillation circuit (OSC1) comprises a ring oscillator forming a feedback loop on the basis of said control signal (RAS1).
Claim 7
Dependent Claim
70 words
The device of claim 4 or 5, further comprising a level detection circuit (VLD) for detecting the level of said back-bias voltage (-Vbb), and wherein said control circuit (G1) generates said operation control signal for making said second oscillation circuit (OSC1) operative on the basis of said control signal during the period in which said first circuit is operative and during the period in which said detection signal is generated.
Claim 8
Dependent Claim
54 words
The device of claim 6 wherein said level detection circuit (VLD) comprises a level shift circuit (Q10 ... Q14) for generating a level-shifted output voltage with respect to said back-bias voltage (-Vbb) upon receiving said back-bias voltage, and a level discrimination circuit (Q15 ... Q17, IVo) receiving the output of said level shift circuit.
Claim 9
Dependent Claim
45 words
The device of claim 7 wherein said level shift circuit comprises a plurality of level shift elements (Q12 ... Q14) each including an insulated gate field effect transistor of diode connection, that are connected in series with one another, and a bias element (Q10, Q11).
Claim 10
Dependent Claim
20 words
The device of claim 7 or 8 wherein said level discrimination circuit comprises a hysteresis circuit (Q15 ... Q17, IVo).
Claim 11
Independent Claim
28 words
The device of any of claims 4 to 9 wherein the oscillation frequency of said first oscillation circuit (OSC2) is lower than that of said oscillation circuit (OSC1).
Claim 12
Independent Claim
26 words
The device of any of claims 1 to 4 wherein said first circuit comprises a memory (MARY) whose operation is controlled by said control signal (RAS1).
Claim 13
Dependent Claim
28 words
The device of claim 11 wherein said memory (MARY) comprises a dynamic type random access memory, and said control signal (RAS1) comprises at least a chip selection signal.
Claim 14
Dependent Claim
87 words
The device of claim 12 wherein said dynamic type random access memory (MARY) is rendered operative at the time of chip selection determined by said chip selection signal (RAS1) and at the time of a refresh operation determined by a refresh control signal (Oref), and said control circuit generates said operation control signal for making said second oscillation circuit (OSC1) operative in synchronism with the operative state of said dynamic type random access memory, on the basis of said chip selection signal and said refresh control signal.
Claim 15
Independent Claim
89 words
The device of any of claims 11 to 13 further comprising a level detection circuit (VLD) detecting the level of said back-bias voltage (-Vbb), and wherein said control circuit generates said operation control signal for making said second oscillation circuit (OSC1) operative during the period in which said dynamic type random access memory (MARY) is made operative on the basis of said chip selection signal (RAS1) and said refresh control signal (φref), and during the period in which the detection signal is generated from said level detection circuit (VLD).
Claim 16
Dependent Claim
67 words
The device of claim 2 wherein said back-bias generation circuit (Vbb-G) comprises a common oscillation circuit (OSC) generating pulse signals to be supplied to said first and second rectification circuits (CPC1, CPC2), said control circuit and said first and second rectification circuits, and said control circuit includes a gate circuit (G7) inhibiting the operation of said second rectification circuit (CPC2) when said first circuit is made inoperative.
Claim 17
Dependent Claim
45 words
The device of claim 15 wherein said gate circuit (G7) is disposed between the output terminal of said oscillation circuit (OSC) and the input terminal of said second rectification circuit (CPC2), and the operation of said gate circuit (G7) is controlled by said control signal.
Claim 18
Dependent Claim
59 words
The device of claim 15 or 16, further comprising a level detection circuit (VLD) detecting the level of said back-bias voltage (-Vbb), and wherein said gate circuit (G7) inhibits the operation of said second rectification circuit (CPC2) when said first circuit is made inoperative and when the detection signal (VD) is not generated from said level detection circuit (VLD).
Claim 19
Dependent Claim
52 words
The device of claim 17 wherein said level detection circuit (V L D) comprises a level shift circuit (Q26 ... Q29) generating an output voltage level-shifted with respect to said back-bias voltage (-Vbb) upon receiving said back-bias voltage, and a level discrimination circuit (IV10) receiving the output of said level shift circuit.
Claim 20
Dependent Claim
53 words
The device of claim 18 wherein said level shift circuit comprises a plurality of level shift elements (Q27 ... Q29) each of which includes an insulated gate field effect transistor which transistors are connected in series with one another, and a bias element (Q26) applying a bias current to said level shift elements.
Claim 21
Dependent Claim
125 words
The device of claim 1 wherein said back-bias voltage generation circuit (Vbb-G) comprises a first capacitor which is pre-charged in response to a first level of a periodic pulse signal and applies a bias potential to be supplied to said substrate gate to a first node in response to a second level of said pulse signal, a first switch circuit connected to said first node and forming a pre-charge path for said first capacitor, a second switch circuit disposed between said first node and said substrate gate and caused to operate substantially complementarily with respect to said first switch circuit, and a second capacitor increasing the pre-charge level of said first capacitor when said first circuit is made operative in response to said control signal.
Claim 22
Dependent Claim
134 words
A semiconductor integrated circuit device comprising: a first circuit including insulated gate field effect transistors (Qm) having a substrate gate to which a back-bias voltage (-Vbb) is applied; a back-bias voltage generation circuit (Vbb-G) generating said back-bias voltage upon receiving pulse signals; a level detection circuit (VLD) comprising a level discrimination circuit, a level shift circuit disposed between an input terminal of said level discrimination circuit and said substrate gate and supplying a voltage level-shifted by a predetermined level with respect to said back-bias voltage to the input of said level discrimination circuit, and a bias element forming a bias current for said level shift circuit; and a gate circuit (G7) controlling said pulse signal to be supplied to said back-bias voltage generation circuit in response to the output of said level discrimination circuit.
Claim 23
Dependent Claim
134 words
A semiconductor integrated circuit device comprising: a first circuit including insulated gate field effect transistors (Qm) having a substrate gate to which a back-bias voltage (-Vbb) is applied; a back-bias voltage generation circuit (Vbb-G) generating said back-bias voltage upon receiving pulse signals; a level detection circuit (VLD) comprising a level discrimination circuit, a level shift circuit disposed between an input terminal of said level discrimination circuit and said substrate gate and supplying a voltage level-shifted by a predetermined level with respect to said back-bias voltage to the input of said level discrimination circuit, and a bias element forming a bias current for said level shift circuit; and a gate circuit (G7) controlling said pulse signal to be supplied to said back-bias voltage generation circuit in response to the output of said level discrimination circuit.
References Cited (Backward Citations)
No citation records indexed.
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