Receiver unit having synchronous pull-in circuit

Claim 2

A receiver unit having a synchronous pull-in circuit, comprising: a demodulator (3) for demodulating a received signal with a carrier; a transversal filter (4) having a roll-off characteristic for transforming the demodulated signal into the form of an impulse response by adjusting its tap coefficients; a timing discriminator (6) for extracting a timing signal contained in the output from the roll-off filter (4); and a decision part (7) for detecting a phase deviation between the thus extracted timing signal and an internal clock by which the receiver unit itself is synchronized, characterized in that the synchronous pull-in circuit is formed by both the decision part (7) and the roll-off filter (4), the roll-off filter (4) being operative to apply a phase shift to the received signal given from the demodulator (3) by adjusting its tap coefficients in accordance with the phase deviation determined by the decision part (7), whereby the timing signal of the received signal is synchronously pulled-in with the internal clock.

Claim 3

A receiver unit having a synchronous pull-in circuit, comprising: an analog/digital (A/D) converter (2) for converting a received signal (S R ) into digital form with a sampling clock; a demodulator (3) for demodulating th output from the A/D converter (2) with a carrier; a transversal filter (4) having a roll-off characteristic for transforming the demodulated signal into the form of an impulse response by adjusting its tap coefficients; a timing discriminator (6) for extracting a timing signal contained in the output from the roll-off filter (4); a decision part (7) for detecting a phase deviation between the thus extracted timing signal and an internal clock by which the receiver unit itself is synchronized; and a phase-locked loop (PLL) part (8) which is controlled by the output from the decision part (7) to produce the internal clock for the generation of the sampling clock to be given to the A/D converter (2), characterized in that the synchronous pull-in circuit is formed by the decision part (7), the roll-off filter (4), and the PLL part (8), the roll-off filter (4) being operative to apply a phase shift to the received signal given from the demodulator (3) by adjusting its tap coefficients in accordance with the phase deviation determined by the decision part (7), also the PLL part (8) being operative to apply a phase jump to the internal clock to shift the sampling phase of the sampling clock, whereby the timing signal of the received signal is synchronized with the internal clock.

Claim 4

A receiver unit having a synchronous pull-in circuit, comprising: an analog/digital (A/D) converter (2) for converting a received signal (S R ) into digital form with a sampling clock; a demodulator (3) for demodulating th output from the A/D converter (2) with a carrier; a transversal filter (4) having a roll-off characteristic for transforming the demodulated signal into the form of an impulse response by adjusting its tap coefficients; a timing discriminator (6) for extracting a timing signal contained in the output from the roll-off filter (4); a decision part (7) for detecting a phase deviation between the thus extracted timing signal and an internal clock by which the receiver unit itself is synchronized; and a phase-locked loop (PLL) part (8) which is controlled by the output from the decision part (7) to produce the internal clock for the generation of the sampling clock to be given to the A/D converter (2), characterized in that the synchronous pull-in circuit is formed by the decision part (7), the roll-off filter (4), and the PLL part (8), the roll-off filter (4) being operative to apply a phase shift to the received signal given from the demodulator (3) by adjusting its tap coefficients in accordance with the phase deviation determined by the decision part (7), also the PLL part (8) being operative to apply a phase jump to the internal clock to shift the sampling phase of the sampling clock, whereby the timing signal of the received signal is synchronized with the internal clock.

Claim 5

A receiver unit according to claim 1 or 2, wherein a line (L 1 ) is connected between the decision part (7) and the roll-off filter (4) to vary the tap coefficients of the roll-off filter (4) in response to the decision output from the decision part (7).

Claim 6

A receiver unit according to claim 3 when dependent upon claim 2, wherein a second line (L 2 ) is connected between the PLL part (8) and the A/D converter (2) to vary the sampling phase by the phase jump, the second line commonly transferring a usual control signal for fine adjustment in frequency of the sampling clock in accordance with a usual error signal defined by the phase deviation of the decision part (7).

Claim 7

A receiver unit according to any one of the preceding claims, wherein the demodulator (3) comprises a real side multiplier (31) and an imaginary side multiplier (32) to produce a real side baseband signal (X) and an imaginary side baseband signal (Y) , respectively; the roll-off filter (4) comprises a real side roll-off filter (40X) and an imaginary side roll-off filter (40Y) to produce real side (RX) and imaginary side (RY) filtered outputs, respectively; the timing discriminator (6) comprises a real side bandpass filter (61), a real side square circuit (63) connected to it, both dealing with the real side filtered output (AX), an imaginary side bandpass filter (62), an imaginary side square circuit (64) connected to it, both dealing with the imaginary side filtered output (AY), an adder (65) for adding both outputs from the real side (63) and imaginary side (64) square circuits, another bandpass filter (66) being operative to receive the output from the adder (64) and produce a real side timing component (TX), and a 90° phase rotation part (67) connected to the output of the other bandpass filter (66) to produce an imaginary side timing component (TY).

Claim 8

A receiver unit according to claim 5, wherein the decision part (7) comprises: a real side polarity decision part (70X) and an imaginary side polarity decision part (70Y) which respectively receive the real side (TX) and imaginary side (TY) timing components, and thereby produce polarity decision data (d 1' d 2 ); an absolute value generator (71) being operative to receive the real side (TX) and imaginary side (TY) timing components and produce the absolute values (|TX|, |TY|) of these timing components; a plurality of multipliers (72 - 1 to 4) which commonly receive the absolute values (|TX|, |TY|) of the timing components, each of which multipliers (72 - 1 to 4) multiplies the absolute value by different values of phase rotation from one another; a plurality of vector decision parts (73 - 1 to 4) receiving the outputs from the multipliers (72 - 1 to 4) for the phase rotation, respectively, and thereby producing phase decision data (d 3 , d 4 , d 5 , d 6 ); and a read-only memory (ROM ) (74) which receives, as an address, the polarity decision data and phase decision data and produces the tap coefficients (C 1 -C n ) specified by these data, which tap coefficients (C 1 -C n ) are supplied to the roll-off filter (4).

Claim 9

A receiver unit according to claim 6, wherein each of the vector decision parts (73 - 1 to 4) comprises: a real side absolute value generator (73b) and an imaginary side absolute value generator (73a) receiving respectively the real side (TX) and imaginary side (TY) outputs given from the corresponding one of the phase rotation multipliers (72); a multiplier (73c) which multiplies the output from the real side absolute value generator (73b) by a predetermined value for applying a predetermined phase rotation to the real side timing component produced from the real side absolute value generator (73b); an adder (73d) being operative to subtract the value from the phase rotation multiplier (73c) of the real side timing component by the value from the imaginary side absolute value generator (73a) of the imaginary side timing component; and a polarity decision part (73e) being operative to receive the output from the adder (73d) for subtraction and to produce the phase decision data (d 3-6 ).

Claim 10

A receiver unit according to claim 6 or 7, wherein the ROM stores the tap coefficient data in relation with each of all the predetermined phase deviations accessed by both the polarity decision data and phase decision data given, as an address, to it.

Claim 11

A receiver unit according to claim 6 or 7, wherein the ROM (101) cooperates with both a random-access memory (102) and an address controller (103), the ROM (101) has in it a first region and a second region, the first region receives, as an address, both the polarity decision data (d l , d 2 ) and the phase decision data (d 3 -d 6 ) and produces a corresponding one of the phase deviation data which is given to the address controller (103), the second region stores in it several sets of the tap coefficients and a corresponding one of the tap coefficient sets is read from it in accordance with the polarity and phase decision data and loaded in the RAM (102), and each tap position of the thus loaded tap coefficient set is shifted, in the RAM (102), by an amount defined by the address controller (103).

Claim 12

A receiver unit according to claim 6 or 7, wherein the ROM (101) cooperates with both a random-access memory (102) and an address controller (103), the ROM (101) has in it a first region and a second region, the first region receives, as an address, both the polarity decision data (d l , d 2 ) and the phase decision data (d 3 -d 6 ) and produces a corresponding one of the phase deviation data which is given to the address controller (103), the second region stores in it a single set of the tap coefficient data, the number of the tap positions for it is set larger than the number of the taps with which the roll-off filter (4) is set up, and the address controller (103) is operative to move the tap positions parallely by an amount determined in accordance with the phase deviation data, and the RAM (102) produces the thus moved tap coefficient data.

Claim 13

A receiver unit according to claim 4 or any one of claims 5 to 10 when dependent upon claim 4, wherein the roll-off filter (4) comprises: series-connected multistage delay circuits (41a-41n); a plurality of multipliers (42a-42n) which multiply respective outputs from the delay circuits by individual tap coefficients (C 1 -C n ) given from the decision part; a rear side adder (121) being operative to add outputs given from the multipliers (42) of the rear side; a front side adder (122) being operative to add outputs given from said multipliers (42) of the front side, the front side adder (122) being operative to further add the result from the rear side adder (121); a multiplier (123) which multiplies the result from the front side adder (122) by a predetermined constant (1/K), and an adder (43) which receives the result from the multiplier (123) with the predetermined constant (I/K) and also the output from the centre side multiplier (42c) located between the rear side (42a, 42b) and front side (42 n-1 , 42 ) multipliers and connected with the delay circuit (41c) of the centre side, to produce the output (RX') to be supplied to the timing discriminator (6), in which each of the tap coefficients given to the rear side (42a, 42b) and front side (42 n-1 , 42 ) multipliers is multiplied in advance by a predetermined constant (K), where K is a positive integer larger than 1.

Claim 14

A receiver unit according to claim 6 when dependent upon claim 2, wherein the PLL part (8) comprises a lead/lag controller (132) and a counter (82) having a clock source (81), the lead/lag controller (132) receiving, on one hand, the error signal (ER) and, on the other hand, the phase devication data (8 0 ) given from the ROM (131) to perform the phase jump and applying an output to the counter (32) which is formed as a frequency divider for the clock given from the clock source (31) with a dividing ratio determined by the output from the lead/lag controller (132).

Claim 15

A receiver unit according to any one of the preceding claims, wherein the demodulator (3) and the roll-off filter (4) are combined together to form a single part.

Claim 16

A receiver unit according to claim 15, wherein the single part is basically formed as a roll-off filter comprising: series-connected multistage delay circuits (41); a plurality of multipliers (42) which multiply respective outputs from the delay circuits (4b) by individual tap coefficients given from the decision part (7); and an adder (121, 122, 123) being operative to add outputs from the multipliers (42) to produce filtered output, in which the tap coefficients are determined to include, whole, coefficients relating to the demodulator, simultaneously.

Claim 17

A receiver unit having a synchronous pull-in circuit, the synchronous pull-in circuit comprised of, as a major part, a transversal filter having a roll-off characteristic, i.e., a roll-off filter, a timing discriminator for extracting a timing signal contained in a received signal, and a decision part for detecting a phase deviation between the thus extracted timing signal and an internal clock by which the receiver unit itself is synchronized, said roll-off filter provided with a plurality of taps, the tap coefficients of which are varied in accordance with said phase deviation, so that said timing signal is synchronized with said internal clock.

Claim 18

A receiver unit having a synchronous pull-in circuit, the synchronous pull-in circuit comprised of, as a major part, a transversal filter having a roll-off characteristic, i.e., a roll-off filter, a timing discriminator for extracting a timing signal contained in a received signal, and a decision part for detecting a phase deviation between the thus extracted timing signal and an internal clock by which the receiver unit itself is synchronized, said roll-off filter provided with a plurality of taps, the tap coefficients of which are varied in accordance with said phase deviation, so that said timing signal is synchronized with said internal clock.

Claim 29

A method as set forth in claim 18 or 20, wherein, in the step of adjusting the relative phase, said phase jump for the adjustment is achieved with every small step of the phase deviation, while said phase shift for the adjustment is achieved with every large step of the phase deviation.