Patent EP0173556A2 successfully refreshed from Google Patents.
EP0173556A2
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EP
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Hierarchical architecture for determining the least recently used cache memory
Assignee: Texas Instruments Inc
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Filing: 1985-08-28
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Granted: —
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Expires: 2005-08-28
Abstract
Abstract A cache memory system includes a set of associative data memories (108), (110), (112) and (114) with associated tag memories (116), (118), (120) and (122). The output of the Tag Memories are input to comparator circuits (144), (146), (148) and (150) to compare the most significant bits therein with the most significant bits on the address bus (124). Each of the tag memories (116)-(122) is directly addressable by either a virtual or a physical address with the most significant bits of each address contained in each tag memory. An LRU controller (172) controls the selection of the data memories (108)-(114) for writing data therein to determine which of the memories is the least recently used one. The LRU controller (172) is interfaced with an RLU memory (176) for storage of LRU data therein. In addition, fault information is stored in a fault memory (184) to prevent the LRU controller (172) from selecting a faulty memory location for writing of data thereto.
Inventors
- 👤 Patrick W. Bosshart
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 14:44
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/126; B; B23; B23K; B23K26/00; B23K26/08; G06F12/0802; G06F12/0864; G06F12/123; G06F12/125; G06F2212/00; G06F2212/10; G06F2212/1032
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
303 words
An associative cache memory architecture for determining the least recently used cache member, comprising: processor means for generating main memory address signals; a main memory having a plurality of memory locations for storing main memory data words; first and second pairs of cache memories, each cache memory in said first and second memory having a tag memory and a data memory; each cache memory responsive to said main address signal to generate an access signal if data corresponding to said main address signal is stored therein, said corresponding data then accessed by said processor means; first steering means for receiving access signals from each of said cache memories in said first pair and determining the least recently used one thereof, said first steering means outputting a first access signal in response to receiving an access signal from said associated cache memory; second steering means for receiving access signals from each of said cache memories in said second pair and determining the least recently used one thereof, said second steering means outputting a second access signal in response to receiving an access signal from either of said associated cache memories; third steering means for receiving said first and second access signals from said first and second steering means and determining which of said first and second pairs of cache memories is the least recently used pair; and means for generating a least recently used signal and applying it to one of said cache memories associated with said least recently used pair and the least recently used one of said cache memories in said least recently used pair, the one of said cache memories associated with said least recently used signal being designated to receive data from said main memory, the remaining ones of said cache memories inhibited from receiving data from said main memory.
Claim 2
Dependent Claim
303 words
An associative cache memory architecture for determining the least recently used cache member, comprising: processor means for generating main memory address signals; a main memory having a plurality of memory locations for storing main memory data words; first and second pairs of cache memories, each cache memory in said first and second memory having a tag memory and a data memory; each cache memory responsive to said main address signal to generate an access signal if data corresponding to said main address signal is stored therein, said corresponding data then accessed by said processor means; first steering means for receiving access signals from each of said cache memories in said first pair and determining the least recently used one thereof, said first steering means outputting a first access signal in response to receiving an access signal from said associated cache memory; second steering means for receiving access signals from each of said cache memories in said second pair and determining the least recently used one thereof, said second steering means outputting a second access signal in response to receiving an access signal from either of said associated cache memories; third steering means for receiving said first and second access signals from said first and second steering means and determining which of said first and second pairs of cache memories is the least recently used pair; and means for generating a least recently used signal and applying it to one of said cache memories associated with said least recently used pair and the least recently used one of said cache memories in said least recently used pair, the one of said cache memories associated with said least recently used signal being designated to receive data from said main memory, the remaining ones of said cache memories inhibited from receiving data from said main memory.
Claim 3
Dependent Claim
159 words
The memory of Claim 1 and further comprising: first means for generating a logic bit having two states and associated with said first steering means, each state of said bit associated with the LRU determination made by said first steering means; second means for generating a logic bit having two states and associated with said second steering means, each state of said bit associated with the LRU determination made by said second steering means; third means for generating a logic bit having two states and associated with said third steering means, each state of said bit associated with the LRU determination made by said third steering means; and means for storing the logic bits generated by said first, second and third bit generating means; said storage means addressable by said main address signal to control said first, second and third steering means in response thereto to determine which of said cache memories is the least recently used one thereof.
Claim 4
Dependent Claim
29 words
The memory of Claim 1 and further comprising outputting a third access signal from said third steering means in response to receiving either said first or second access signal.
Claim 5
Dependent Claim
189 words
The memory of Claim 1 wherein said means for generating said least recently used signal comprises: means for generating a first steering signal in response to the least recently used determination of said third steering means, said first steering signal output to the one of said pairs determined as least recently used; means for generating a second steering signal associated with said second steering means in response to receiving said first steering signal, said second steering signal output to the one of said caches associated with said second steering means and determined to be the least recently used one thereof; means for generating a third steering signal associated with said first steering means in response to receiving said first steering signal, said third steering signal associated with the least recently used one of said cache memories associated with said first pair as determined by said first steering means; and said first steering signal activated by said generating means and one of said second and third steering signals activated by said first steering signal, the activated one of said second and third steering signals being said least recently used signal.
Claim 6
Dependent Claim
132 words
The memory of Claim 1 wherein said tag and data memories in each of said cache memories have a plurality of addressable locations therein such that all of said cache memories are simultaneously addressable by said main address signal, said first, second and third steering means determining the least recently used one of said cache memories and the address location therein in response to said main address signal, and further comprising: means for storing the least recently used determination of said first, second and third steering means in association with the corresponding one of said main address signals; and means for accessing said stored least recently used determination by said generating means such that said least recently used signal can be generated corresponding to the generated one of said main address signals.
Claim 7
Dependent Claim
176 words
The memory of Claim 5 wherein said means for storing comprises: a first logic bit associated with said first steering means and each addressable location in said cache memories, said first logic bit having two states, the state thereof determined by which of said associated cache memories is determined as being the least recently used one thereof; a second logic bit associated with said second steering means for each addressable location in said cache memories, said second logic bit having two states, each state associated with the least recently used determination of said associated cache memories; a third logic bit associated with said third steering means and each addressable location in said cache memories, said third logic bit having two states, each state associated with the least recently used determination made by said third steering means as to said first and second pairs; and a memory having a plurality of locations addressable by said main address signal, said first, second and third logic bits stored in a memory location corresponding to the associated main address signal.
Claim 8
Dependent Claim
47 words
The memory of Claim 5 and further comprising means for storing information regarding defective ones of said addressable locations in each of said caches as the least recently used one of said caches when the addressable location therein is determined to be defective by said storage means.
Claim 9
Dependent Claim
97 words
The memory of Claim 7 wherein said means for storing comprises: a memory having a plurality of locations corresponding to the addressable locations in said cache memories; said memory having stored therein a fault logic bit corresponding to each of said addressable locations in each of said cache memories, each of said logic bits having a fault state and a non-fault state; and means for addressing said memory by said main address signal for output of said associated fault bits to inhibit least recently used determination of when said associated fault bit is in the fault state.
References Cited (Backward Citations)
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