Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
296 words
A complementary Bi-MIS gate circuit, characterized in a first CMIS circuit having a first PMIS transistor (P 1 ) connected to a high potential source, a first NMIS transistor (N i ) connected to a low potential source, and a first impedance element (R 1 ) inserted between said first PMIS transistor (P 1 ) and said first NMIS transistor (N 1 ) ; a second CMIS circuit having a second PMIS transistor (P 2 ) connected to said high potential source, a second NMIS transistor (N 2 ) connected to said low potential source, and a second impedance element (R 2 ) inserted between said second PMIS transistor (P 2 ) and said second NMIS transistor (N 2 ); a signal input terminal (TM I ) operatively connected to the gate terminals of said first and second PMIS and NMIS transistors (P 1 , P 2 , N 1 , N 2 ); a load driving invertor having a vertically structured pull-up bipolar transistor (T 1 ) and a vertically structured pull-down bipolar transistor (T 2 ), said pull-up and pull-down bipolar transistors (T 1 , T 2 ) being connected in series; the base terminal of said pull-up bipolar transistor (T 1 ) being operatively connected to the connecting point (B) of said first PMIS transistor (P 1 ) and said first impedance element (R 1 ); the base terminal of said pull-down bipolar transistor (T 2 ) being operatively connected to the connecting point (C) of said second NMIS transistor (N 2 ) and said second impedance element (R 2 ); and a signal output terminal (TM O ) operatively connected to the connecting point of said pull-up and pull-down bipolar transistors (T 1 , T 2 ) to said signal output terminal.
Claim 2
Dependent Claim
296 words
A complementary Bi-MIS gate circuit, characterized in a first CMIS circuit having a first PMIS transistor (P 1 ) connected to a high potential source, a first NMIS transistor (N i ) connected to a low potential source, and a first impedance element (R 1 ) inserted between said first PMIS transistor (P 1 ) and said first NMIS transistor (N 1 ) ; a second CMIS circuit having a second PMIS transistor (P 2 ) connected to said high potential source, a second NMIS transistor (N 2 ) connected to said low potential source, and a second impedance element (R 2 ) inserted between said second PMIS transistor (P 2 ) and said second NMIS transistor (N 2 ); a signal input terminal (TM I ) operatively connected to the gate terminals of said first and second PMIS and NMIS transistors (P 1 , P 2 , N 1 , N 2 ); a load driving invertor having a vertically structured pull-up bipolar transistor (T 1 ) and a vertically structured pull-down bipolar transistor (T 2 ), said pull-up and pull-down bipolar transistors (T 1 , T 2 ) being connected in series; the base terminal of said pull-up bipolar transistor (T 1 ) being operatively connected to the connecting point (B) of said first PMIS transistor (P 1 ) and said first impedance element (R 1 ); the base terminal of said pull-down bipolar transistor (T 2 ) being operatively connected to the connecting point (C) of said second NMIS transistor (N 2 ) and said second impedance element (R 2 ); and a signal output terminal (TM O ) operatively connected to the connecting point of said pull-up and pull-down bipolar transistors (T 1 , T 2 ) to said signal output terminal.
Claim 3
Dependent Claim
109 words
The complementary Bi-MIS gate circuit according to claim 1, characterized in a third PMIS transistor (P 3 ) connected between said base terminal of said pull-up bipolar transistor (T 1 ) and said high potential source; a third NMIS transistor (N 3 ) connected between said base terminal of said pull-down bipolar transistor (T 2 ) and said low potential source; means (TM C ) for feeding an enable signal to the gate terminal of said third PMIS transistor (P 3 ); and means (TM C ; I) for feeding the inverted signal of said enable signal to the gate terminal of said third NMIS transistor (N 3 ).
Claim 4
Dependent Claim
105 words
The complementary Bi-MIS gate circuit according to claim 2 characterized in that a fourth PMIS transistor (P 4 ) connected between said second PMIS transistor (P 2 ) and said second impedance element (R2); a fourth NMIS transistor (N 4 ) connected between said first NMIS transistor (N 1 ) and said first impedance element (R 1 ); means (TM C' I) for feeding said inverted signal of said enable signal to the gate terminal of said fourth PMIS transistor (P 4 ); and means (TM C ) for feeding said enable signal to the gate terminal of said fourth NMIS transistor (N 4 ).
Claim 5
Dependent Claim
56 words
The complementary Bi-MIS gate circuit according to any one of claims 1 to 3, characterized in that said PMIS transistor comprises a PMOS transistor (P 1 , P 2 , P 3 , P 4 ) and said NMIS transistor comprises a NMOS transistor (N 1 , N 2 , N 3 , N 4 ).
Claim 6
Dependent Claim
29 words
The complementary Bi-MIS gate circuit according to any one of claims 1 to 4, characterized in that said impedance element comprises a resistor (R 1 , R 2 ).