Patent EP0172342A2 successfully refreshed from Google Patents.
EP0172342A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Bus control gate array
Assignee: EMC Corp
•
Filing: 1985-06-13
•
Granted: —
•
Expires: 2005-06-13
Abstract
Abstract In a computer having a central processing unit (CPU) (9), a common bus (1, 3, 5), a plurality of input and output devices which are connected to the common bus (1, 3, 5) and which have an intrinsic I/O device address, individually, and a bus control gate array, the bus control gate array according to the present invention includes an I/O device address decoder (47). The I/O device address decoder 47 comprises a plurality of gates (53, 55...57) and decodes an I/O device address supplied from the CPU (9) to produce a control signal for selecting the designated I/0 device thereto.
Inventors
- 👤 Shigemi Arima
- 👤 Takashi Nakada
- 👤 Kazuhiro Miyashita
- 👤 Etsuo Iijima
- 👤 Hideji Katayama
- 👤 Yoshihiko Wadano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 17:16
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
128 words
In a data processing system having a common bus (1, 3, 5), a plurality of input/output devices (13, 15, 16, 19, 23, 33, 37) connected to said common bus and assigned with different input/output device addresses, a bus control gate array (7) for controlling said common bus, and a central processing element (9) connected to said common bus (1, 3, 5) to control said plurality of input/output devices and said bus control gate array, a bus control gate array characterized by comprising input/output device select signal generating means (47) for decoding an input/output device address signal supplied from said central processing element (9) and selecting one of said plurality of input/output devices (13, 15, 16, 19, 23, 33, 37) in accordance with the decoded input/output device address signal.
Claim 2
Dependent Claim
128 words
In a data processing system having a common bus (1, 3, 5), a plurality of input/output devices (13, 15, 16, 19, 23, 33, 37) connected to said common bus and assigned with different input/output device addresses, a bus control gate array (7) for controlling said common bus, and a central processing element (9) connected to said common bus (1, 3, 5) to control said plurality of input/output devices and said bus control gate array, a bus control gate array characterized by comprising input/output device select signal generating means (47) for decoding an input/output device address signal supplied from said central processing element (9) and selecting one of said plurality of input/output devices (13, 15, 16, 19, 23, 33, 37) in accordance with the decoded input/output device address signal.
Claim 3
Dependent Claim
40 words
A bus control gate array according to claim 1, characterized in that said input/output device select signal generating means comprises a plurality of logic gates (53, 55...57) and said bus control gate array comprises a highly integrated one-chip semiconductor device.
Claim 4
Dependent Claim
59 words
A bus control gate array according to claim 1, characterized by further comprising memory select signal generating means (63) for decoding a memory address signal from said central processing element (9) and for generating a memory select signal URMO, URM1, URM2, URM3, VRO, VR1 for selecting one of said memory bank in accordance with the decoded memory address signal.
Claim 5
Dependent Claim
21 words
A bus control gate array according to claim 1 or 2, characterized by further comprising a highly integrated one-chip semiconductor device.
Claim 6
Dependent Claim
76 words
A bus control gate array according to claim 3, characterized in that said memory unit comprises a random access memory (15) and a read only memory (16) which respectively have a plurality of memory banks, and said memory select signal generating means (63) generates a read only memory select signal (UROM) for selecting said read only memory in addition to said memory select signal (URMO, URM1, URM2, URM3) for selecting the one of said memory banks.
Claim 7
Dependent Claim
40 words
A bus control gate array according to claim 3 or 4, characterized in that said memory select signal generating means (63) has a plurality of logic gates, and said bus control gate array comprises a one-chip highly integrated semiconductor element.
Claim 8
Dependent Claim
77 words
A bus control gate array according to claim 3, 4, 5 or 6, characterized in that said memory unit comprises a plurality of memory banks (151, 152' 153' 154) each of which has a plurality of memory chips, and a chip selector for selecting any one of said plurality of memory chips, and said bus controller comprises memory bank selecting means (63) for generating a memory bank select signal for selecting any one of said memory banks.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.