Patent EP0171859A2 successfully refreshed from Google Patents.
EP0171859A2
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EP
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Memory access control device for implementing guarded regions in a memory, and memory provided with such memory access control device
Assignee: Koninklijke Philips NV
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Filing: 1985-08-09
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Granted: —
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Expires: 2005-08-09
Abstract
Abstract In a virtual memory system, a guarded region allows access to protected code and data without intervention from a processor's operating system by redefining regions of an address space with reference to gates indicating points of entry for those regions. A non-hierarchial access path in the form of tree-like structure permits a process to access resources and data while controlling access thereto and return therefrom.
Inventors
- 👤 Martin Freeman
- 👤 Cecil Hertz Kaplinsky
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1458; G06F12/1491
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
217 words
A memory access control device for use in a data processing system, said device having a first connection for connecting to a memory for storing information and for being partitioned into a plurality of identifiable address spaces, said device having a second connection for connecting to a central processing unit for therefrom receiving virtual address information, characterized in that said device comprises: first programmable means to partition the virtual address space of at least one process executable on said central processing unit into a least two regions of variable lengths; second programmable means to allocate instructions and data to respective ones of said regions; third programmable means to receive information and thereby access respective levels of protection and associated levels of access permission to each of said respective regions; fourth programmable means to receive information for assigning entry points to sub-spaces of said address space; address mapping means to map virtual addresses within said respective regions into physical addresses within said respective sub-spaces of physical memory; defining means for within a predetermined region redefining the contents of an virtual address space associated with said region by reference to a gate structure that defines a further guarded region which is conditionally accessible and which gate structure also defines at least one fixed entry point for said guarded region.
Claim 2
Dependent Claim
217 words
A memory access control device for use in a data processing system, said device having a first connection for connecting to a memory for storing information and for being partitioned into a plurality of identifiable address spaces, said device having a second connection for connecting to a central processing unit for therefrom receiving virtual address information, characterized in that said device comprises: first programmable means to partition the virtual address space of at least one process executable on said central processing unit into a least two regions of variable lengths; second programmable means to allocate instructions and data to respective ones of said regions; third programmable means to receive information and thereby access respective levels of protection and associated levels of access permission to each of said respective regions; fourth programmable means to receive information for assigning entry points to sub-spaces of said address space; address mapping means to map virtual addresses within said respective regions into physical addresses within said respective sub-spaces of physical memory; defining means for within a predetermined region redefining the contents of an virtual address space associated with said region by reference to a gate structure that defines a further guarded region which is conditionally accessible and which gate structure also defines at least one fixed entry point for said guarded region.
Claim 3
Dependent Claim
35 words
A device as claimed in claim 1, wherein a gate comprises a gate module for performing gate operations and a gate descriptor having a seg- mnt table pointer, a segment length, and an entry point.
Claim 4
Dependent Claim
24 words
A device as claimed in claim 1 or 2, wherein each region is defined by an associated segment table pointer and segment table length.
Claim 5
Dependent Claim
22 words
A device as claimed in claim 3, wherein the address space of a process is changed by redefinition of its segment table.
Claim 6
Dependent Claim
19 words
A device as. claimed in claim 4, wherein one segment of an address space is a list of gates.
Claim 7
Independent Claim
28 words
A device as claimed in any of claims 1 to 5, further including a stack for storing return information to be used upon exit from the guarded region.
Claim 8
Independent Claim
22 words
A device as claimed in any of claims 1 through 6, wherein said device is contained in a single integrated circuit chip.
Claim 9
Dependent Claim
25 words
A memory interconnected to a device as claimed in any of claims 1 through 7, wherein said memory comprises a plurality of said address subspaces.
Claim 10
Dependent Claim
18 words
A memory system having a memory as claimed in claim 8, wherein said memory supports a paged organisation.
Claim 11
Dependent Claim
18 words
A memory system having a memory as claimed in claim 8, wherein said memory supports a segmented organisation.
Claim 12
Dependent Claim
39 words
A computer system having a memory interconnected to a device as claimed in any of claims 1 through 7, and furthermore a central processor interconnected to said memory and said device for forwarding virtual address data to said device.
Claim 13
Dependent Claim
17 words
A data processing system comprising a plurality of computer systems claimed in claim 11 for parallel processing.
References Cited (Backward Citations)
No citation records indexed.
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