Patent EP0171088A2 successfully refreshed from Google Patents.
EP0171088A2
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EP
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Microprocessor with execution unit independently put into standby condition
Assignee: NEC Corp
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Filing: 1985-08-12
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Granted: —
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Expires: 2005-08-12
Abstract
Abstract A microprocessor of CMOS structure which includes at least an execution unit and a control unit including an instruction register adapted to receive and store instructions to be executed by the microprocessor and an instruction decoder receiving the instruction from the instruction register and outputting a control signal. Furthermore, the processor comprises a second instruction decoder receiving at least a portion of the instruction applied from the instruction register to the first instruction decoder so as to supply a standby control signal to the execution unit.
Inventors
- 👤 Kouichi Yamada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 05:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3287; G06F9/22; G06F9/226; G06F9/30003; G06F9/30076; G06F9/30083; G06F9/30145; G06F9/30181; G06F9/30185; G06F9/3836; G06F9/3885; Y; Y02; Y02D; Y02D10/00; Y02D30/00; Y02D30/50
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
88 words
A microprocessor of CMOS structure which includes at least an execution unit and a control unit including an instruction register adapted to receive and store instructions to be executed by the microprocessor and an instruction decoder receiving the instruction from the instruction register and outputting at least one control signal, wherein the improvement comprises a second instruction decoder receiving at least a portion of the instruction applied from the instruction register to the first instruction decoder so as to supply a standby control signal to the execution unit.
Claim 2
Dependent Claim
88 words
A microprocessor of CMOS structure which includes at least an execution unit and a control unit including an instruction register adapted to receive and store instructions to be executed by the microprocessor and an instruction decoder receiving the instruction from the instruction register and outputting at least one control signal, wherein the improvement comprises a second instruction decoder receiving at least a portion of the instruction applied from the instruction register to the first instruction decoder so as to supply a standby control signal to the execution unit.
Claim 3
Dependent Claim
42 words
A microprocessor as claimed in Claim 1 wherein the execution unit is adapted to put only a portion of the execution unit in the standby mode, and to return that portion to the operation mode in response to the standby control signal.
Claim 4
Dependent Claim
25 words
A microprocessor as claimed in Claim 2 wherein the portion of the execution unit put in the standby mode is a microprogram ROM read-out circuit.
Claim 5
Dependent Claim
33 words
A microprocessor as claimed in Claim 2 wherein the portion of the execution unit put in the standby mode is a carry lookahead circuit in an arithmetic logic circuit of the execution unit.
Claim 6
Dependent Claim
46 words
A microprocessor as claimed in Claim 1 further including a microprogram ROM read controller adapted to detect an END microinstruction and to generate a halt signal and wherein the execution unit is adapted to be put into the standby mode in response to the halt signal.
Claim 7
Dependent Claim
42 words
A microprocessor as claimed in Claim 5 further including a microprogram ROM read-out circuit which is associated to a microprogram ROM and adapted to be rendered operable in response to the standby control signal and non-operable in response to the halt signal.
Claim 8
Dependent Claim
64 words
A microprocessor as claimed in Claim 5 further including carry lookahead circuit in the execution unit and a carry lookahead biasing circuit which is associated to a carry lookahead circuit and adapted to supply a bias current to the carry lookahead circuit in response to the standby control signal and to stop the supply of the bias current in response to the halt signal.
Claim 9
Dependent Claim
13 words
A microprocessor as claimed in Claim 1 wherein the microprocessor is a coprocessor.
Claim 10
Dependent Claim
30 words
A microprocessor as claimed in Claim 8 wherein the second instruction decoder is -adapted to receive the most significant plural bits of the instruction loaded to the first instruction decoder.
Claim 11
Dependent Claim
100 words
A microprocessor as claimed in Claim 9 wherein the instruction loaded to the first instruction decoder includes the most significant plural bits which indicates whether a given instruction is directed to the coprocessor and the next least significant plural bits which designates whether the given instruction needs read of microprogram, and wherein the second instruction decoder includes a first NOR gate receiving the above most significant plural bits, a second NOR gate receiving the above next least significant plural bits and an AND circuit receiving the outputs of the first and second NOR gates for generating the standby cancel signal.
Claim 12
Dependent Claim
55 words
A microprocessor as claimed in Claim 10 further including a microprogram ROM read controller adapted to detect an END microinstruction by detecting the most significant plural bits of microinstructions and to generate a halt signal and wherein the execution unit is adapted to be put into the standby mode in response to the halt signal.
Claim 13
Dependent Claim
41 words
A microprocessor as claimed in Claim 11 further including a microprogram ROM read-out circuit which is associated to a microprogram ROM and adapted to be rendered operable in response to the standby cancel signal and non-operable in response to the-halt signal.
Claim 14
Dependent Claim
60 words
A microprocessor as claimed in Claim 11 further including carry lookahead circuit in the execution unit and a carry lookahead biasing circuit which is associated to a carry lookahead circuit and adapted to supply a bias voltage to the carry lookahead circuit in response to the standby cancel signal and to make it non-opertable in response to the halt signal.
References Cited (Backward Citations)
No citation records indexed.
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