Patent EP0170525A2 successfully refreshed from Google Patents.
EP0170525A2
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EP
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Cache hierarchy design for use in a memory management unit
Assignee: Texas Instruments Inc
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Filing: 1985-07-31
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Granted: —
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Expires: 2005-07-31
Abstract
Abstract A cache hierarchy to be managed by a memory management unit (MMU) (52) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache (68) backed up by a virtual address cache (85) to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache (75) is combined with a large virtual address cache (70). The provision of a logical address cache (68) enable reference count management to be done completely by the controller of the virtual address cache (85) and the memory management processor (54) in the MMU (52). Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU(50)-MMU (52) interface is released as soon as the access to the logical address cache (68) is completed.
Inventors
- 👤 Satish M. Thatte
- 👤 Donald W. Oxley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 17:13
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1063; G06F12/0802; G06F12/0864
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
114 words
A memory system for use in association with a CPU, having a plurality of binding registers interfacing the memory system to the CPU, comprising: a logical address space addressible by a pair comprising a binding register identifier and an index indicating a cell in a block bound to the binding register identified by the binding register identifier; a logical address cache means associated with the binding registers and addressed by the address pair applied thereto; a virtual address space onto virtual addresses of which said address pair is mapable; means for mapping said address pair onto virtual addresses of said virtual address space; and a virtual address cache means addressed by the virtual addresses.
Claim 2
Dependent Claim
114 words
A memory system for use in association with a CPU, having a plurality of binding registers interfacing the memory system to the CPU, comprising: a logical address space addressible by a pair comprising a binding register identifier and an index indicating a cell in a block bound to the binding register identified by the binding register identifier; a logical address cache means associated with the binding registers and addressed by the address pair applied thereto; a virtual address space onto virtual addresses of which said address pair is mapable; means for mapping said address pair onto virtual addresses of said virtual address space; and a virtual address cache means addressed by the virtual addresses.
Claim 3
Dependent Claim
30 words
The memory system of claim 1 wherein said logical address cache means comprises a logical cache map for addressing the logical address cache means in response to an address pair.
Claim 4
Dependent Claim
43 words
The memory system of claim 2 wherein said logical address cache means further comprises a binding resolution map to which the binding register identifier is applied for producing an output to select a cache map partition for addressing a logical address cache partition.
Claim 5
Dependent Claim
36 words
The memory system of claim 3 further comprising a cache map for said virtual address cache means for addressing the virtual address cache means in response to virtual addresses produced by said address pair mapping means.
Claim 6
Dependent Claim
82 words
The memory system of claim 4 wherein said virtual address cache means comprises two sets of virtual cache memories, two cache maps, each associated with a respective one of said two cache memories, and two comparators, each associated with a respective one of said two cache maps, to compare at least a portion of the virtual address applied to said virtual address cache means with selected contents of said cache maps to produce an output indicating wheterh a cache hit has occurred.
Claim 7
Dependent Claim
62 words
The memory system of claim 4 wherein said logical address cache means comprises a logical address cache partitioned into a plurality of partitions, the number of partitions corresponding to the number of binding registers, and wherein said logical cache map is partitioned into a plurality of partitions, the number of segments corresponding to the number of partitions of said logical address cache.
Claim 8
Dependent Claim
121 words
A memory system for association with a CPU comprising: a physical memory; binding register means for interfacing the physical memory to the CPU for limiting the CPU to access only a logical address space representing said physical memory with logical addresses generated by said user processor; a logical address cache associated with said binding register means for receiving logical addresses, and responsive to which said logical address cache provides selected information cached therewithin; means associated with the binding register means for translating logical addresses into virtual addresses representing a virtual address space representing said physical memory; and a virtual address cache to which said virtual addresses are applied and responsive to which said virtual address cache provides selected information cached therewithin.
Claim 9
Dependent Claim
121 words
A memory system for association with a CPU comprising: a physical memory; binding register means for interfacing the physical memory to the CPU for limiting the CPU to access only a logical address space representing said physical memory with logical addresses generated by said user processor; a logical address cache associated with said binding register means for receiving logical addresses, and responsive to which said logical address cache provides selected information cached therewithin; means associated with the binding register means for translating logical addresses into virtual addresses representing a virtual address space representing said physical memory; and a virtual address cache to which said virtual addresses are applied and responsive to which said virtual address cache provides selected information cached therewithin.
Claim 10
Dependent Claim
161 words
The memory system of claim 7 wherein said logical address cache comprises a cache memory, a cache map and a binding resolution map, said binding resolution map receiving logical address for application to said cache map; said cache map containing an identification of the contents of the cache memory, means for addressing said cache memory, and means for indicating cache hits and cache misses upon the application of at least a portion of the logical addresses to said binding resolution map, and said cache map having memory elements partitioned to be arrangable whereby each partition corresponds to a respective binding register, and is addressible by said binding resolution map. 9. The memory system of claim 8 wherein said virtual address cache comprises at least one virtual cache memory and a virtual cache map, said virtual cache map receiving virtual addresses translated from said logical addresses and addressing said at least one virtual cache memory if the address produces a cache hit.
Claim 11
Dependent Claim
162 words
A memory system for association with a CPU comprising: a memory management unit, comprising: a main memory; a binding register unit for interfacing the main memory to the CPU, including: means comprising a plurality of binding registers for translating logical and virtual addresses between the CPU and the main memory; each logical addresses including a register pair (r, index), wherein "r" represents a binding register identifier and "index" represents an index of a cell in a memory block bound to the binding register indicated by "r"; and a logical address cache to which logical addresses are applied, and responsive to which said logical address cache provides selected information cached therewithin; a virtual address cache to which said virtual addresses are applied and responsive to which said virtual address cache provides selected information cached therewithin; means for translating virtual addresses to real addresses for application to said main memory; and a memory management processor for controlling the operation of the memory management unit.
Claim 12
Dependent Claim
162 words
A memory system for association with a CPU comprising: a memory management unit, comprising: a main memory; a binding register unit for interfacing the main memory to the CPU, including: means comprising a plurality of binding registers for translating logical and virtual addresses between the CPU and the main memory; each logical addresses including a register pair (r, index), wherein "r" represents a binding register identifier and "index" represents an index of a cell in a memory block bound to the binding register indicated by "r"; and a logical address cache to which logical addresses are applied, and responsive to which said logical address cache provides selected information cached therewithin; a virtual address cache to which said virtual addresses are applied and responsive to which said virtual address cache provides selected information cached therewithin; means for translating virtual addresses to real addresses for application to said main memory; and a memory management processor for controlling the operation of the memory management unit.
Claim 13
Dependent Claim
111 words
The memory system of claim 10 wherein said address cache comprises a cache memory, a cache map and a binding resolution map, said binding resolution map receiving logical address for translation to a cache map address applied to said cache map; said cache map containing identification of the contents of the address cache, means for addressing said memory cache, and means for indicating a cache hit and a cache miss upon the application of a logical address to said binding resolution map, and said memory map having memory elements partitioned to be arrangable whereby each partition can correspond to a respective binding register, and addressible by indications from said cache map.
Claim 14
Dependent Claim
44 words
The memory system of claim 11 wherein said virtual address cache comprises at least one cache memory and a cache map, said cache map receiving virtual addresses translated from said logical addresses and addressing said cache memory if the address produces a cache hit.
Claim 15
Dependent Claim
110 words
A memory system for association with a CPU comprising: a memory management unit, comprising: a main memory; a binding register unit for interfacing the main memory to the CPU, including: means comprising a plurality of binding registers for translating logical and virtual addresses between the CPU and the main memory; each logical addresses including a register pair (r, index), wherein "r" represents a binding register identifier and "index" represents an index of a cell in a memory block bound to the binding register indicated by "r" and a logical address cache to which logical addresses are applied, and responsive to which said logical address cache provides selected information cached therewithin*
Claim 16
Dependent Claim
110 words
A memory system for association with a CPU comprising: a memory management unit, comprising: a main memory; a binding register unit for interfacing the main memory to the CPU, including: means comprising a plurality of binding registers for translating logical and virtual addresses between the CPU and the main memory; each logical addresses including a register pair (r, index), wherein "r" represents a binding register identifier and "index" represents an index of a cell in a memory block bound to the binding register indicated by "r" and a logical address cache to which logical addresses are applied, and responsive to which said logical address cache provides selected information cached therewithin*
Claim 17
Dependent Claim
111 words
The memory system of claim 13 wherein said logical cache comprises a cache memory, a cache map and a binding resolution map, said binding resolution map receiving logical address for translation to a cache map address applied to said cache map; said cache map containing identification of the contents of the memory cache, means for addressing said memory cache, and means for indicating a cache hit and a cache miss upon the application of a logical address to said binding resolution map, and said memory map having memory elements partitioned to be arrangable whereby each partition can correspond to a respective binding register, and addressible by indications from said cache map.
References Cited (Backward Citations)
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