Transmission systems

Claim 2

An information transmission system, in which digital data is conveyed in a number of successively-occurring fixed-duration envelopes each of which provides the-capacity for a number of successive bit frames, in which the system conveys both circuit-switched intelligence and packet-switched intelligence, in which priority is given to circuit-switched traffic, which is conveyed in bit frames at the commencement of each said envelope, in which each said envelope embraces a number of bits greater than that needed to handle the maximum number of simultaneous circuit-switched connections to be provided for, in which the traffic being handled by the system is continuously monitored to assess how much circuit-switched traffic is currently being handled, and in which the capacity not needed to handle circuit-switched traffic is available to handle packet-switched traffic.

Claim 3

A system as claimed in claim 1, in which the transmitter includes a set of buffers, one per circuit-switched channel and a buffer for packet-switched traffic, in which the output of all of said buffers are connected to the transmission medium via a multiplexer, in which each said buffer which is in use is loaded from a channel which it serves, and in which the contents of said buffers for circuit-switched traffic are conveyed to the multiplexer under control of a control circuit at appropriate times in the system cycle, whereafter as much of the waiting packet traffic as can be dealt with in the same envelope is conveyed from the packet buffer via the multiplexer to the transmission medium.

Claim 4

A system as claimed in claim 2, in which the frames are separated one from the other by flags each of which includes a block of x consecutive 1 bits, and in which to prevent flag simulation any group of (x - 1) 1 bits has a 0 bit inserted thereafter.

Claim 5

An information transmission system, in which digital data is conveyed in a number of successively-occurring fixed-duration envelopes each of which provides the capacity for a number of successive bit frames, in which the system conveys both circuit-switched intelligence and packet-switched intelligence, priority being given to circuit-switched traffic which is conveyed in one or more contiguous bit frames at the commencement- of each said envelope, in which the system's transmitter includes a set of buffers one for each of a number of possible circuit-switched channels, a buffer for packet-switched traffic, connections over which each said buffer which is in use is loaded from a channel which it serves, further connections via which the outputs of all of said buffers are connected to the transmission medium via a multiplexer, a control circuit under whose control the contents of the buffers for circuit-switched traffic are conveyed to the multiplexer and therefrom to the transmission medium at appropriate times in the system cycle, and monitoring means for the traffic being handled which ensures that after said circuit-switched traffic has been handled such of the waiting packet-switched traffic as can be dealt with in the same envelope is conveyed from the packet buffer via the multiplexer to the transmission medium, whereby such capacity as is not needed to handle circuit-switched traffic is available to handle packet-switched traffic.

Claim 6

An information transmission system, in which digital data is conveyed in a number of successively-occurring fixed-duration envelopes each of which provides the capacity for a number of successive bit frames, in which the system conveys both circuit-switched intelligence and packet-switched intelligence, priority being given to circuit-switched traffic which is conveyed in one or more contiguous bit frames at the commencement- of each said envelope, in which the system's transmitter includes a set of buffers one for each of a number of possible circuit-switched channels, a buffer for packet-switched traffic, connections over which each said buffer which is in use is loaded from a channel which it serves, further connections via which the outputs of all of said buffers are connected to the transmission medium via a multiplexer, a control circuit under whose control the contents of the buffers for circuit-switched traffic are conveyed to the multiplexer and therefrom to the transmission medium at appropriate times in the system cycle, and monitoring means for the traffic being handled which ensures that after said circuit-switched traffic has been handled such of the waiting packet-switched traffic as can be dealt with in the same envelope is conveyed from the packet buffer via the multiplexer to the transmission medium, whereby such capacity as is not needed to handle circuit-switched traffic is available to handle packet-switched traffic.

Claim 7

A system as claimed in claim 4, and which includes monitoring means which monitors the bit stream which leaves the multiplexer, first insertion means under control of the monitoring means and arranged to insert flag bytes into the bit stream to separate said frames one from the other, each said flag byte being formed by the bit combination 01111110, and second insertion means also under control of the monitoring means and arranged to insert a zero bit after any occurrence of five successive 1 bits in the intelligence bit stream, thus ensuring that the bit stream is unable to incorrectly simulate a flag byte.

Claim 8

A receiver for a system as claimed in claim 5, and which includes monitoring means which monitors the incoming bit stream from a remote transmitter, removal means under the control of said monitoring means and adapted to remove both the flag bytes and the inserted zero bits from said bit stream, a demultiplexer to which the bit stream outputted from the monitoring means is applied, a set of circuit-switched buffers and a packet-switched buffer, and control means which routes the intelligence via the demultiplexer to the appropriate one of said buffers.