Abstract A write clock pulse generator (10) is disclosed, in which a horizontal synchronizing signal is separated from an input video signal and supplied to a PLL (phase locked loop) circuit (3) to form a first clock with the frequency of nf H (n is an integer), a color burst signal is separated from the input video signal and used to drive a gate type variable oscillator (14) to thereby form a second clock synchronized in phase with the color burst signal and whose average frequency is nf H , a difference between the pulse widths of the clocks resulting from counting down the first and second clocks to 1/M and the frequency of the variable oscillator (14) is controlled by the compared output therebetween, whereby to produce a second clock synchronized in phase with the color burst signal and the frequency of which is n times the horizontal synchronizing signal.
'A write clock pulse generator/for a time base corrector having a phase locked oscillator (3) responsive to a horizontal synchronizing pulse derived from a reproduced video signal for generating a first clock pulse having a time axis change same as that of said horizontal synchronizing pulse, a frequency of said first clock pulse being n times (n is an integer) the frequency of said horizontal synchronizing pulse, a burst signal separating circuit/for separating a color burst signal from said reproduced video signal, and a generating circuit responsive to said first clock pulse and said separated color burst signal for generating a write clock pulse, the phase and frequency of which are locked to those of said separated color burst signal and said horizontal synchronizing pulse, respectively characterized by a) a pulse signal generator (15) responsive to said color burst signal for generating a control pulse signal having a pulse width corresponding to a predetermined wave length of said color burst signal, said control pulse signal being in phase with said color burst signal: b) start-stop oscillator (14) responsive to a generation of said control pulse signal for generating a second clock pulse the phase of which is in phase with said control pulse signal; (11,16) c) first and second frequency dividers/connected to said phase locked oscillator (3) and said start-stop oscil-(14) lator/and for frequency-dividing said first and second clock pulses; d) a synchronous circuit (12) responsive to a generation of said control pulse for synchronizing dividing (11,16) operations of said first and second frequency dividers; (20) e) a comparator/for comparing pulse widths of output pulsesl (p 1 ,p 2 ) of said first and second frequency dividers (11,16); and (17) f) a control circuit/responsive to an output signal of said comparator (20) for controlling a frequency of said said comparator (20) for controlling a frequency of said start-stop oscillator(14).
Claim 3
Dependent Claim
31 words
The write clock pulse generator according to claim 1, (16) characterized in that a dividing ratio of said first frequency divider/ is equal to that of said second frequency divider (11).
Claim 4
Dependent Claim
22 words
The write clock pulse generator according to claim 2, characterized in that said comparator (20) is of a charge pump type comparator.
Claim 5
Dependent Claim
115 words
The write clock pulse generator according to claim 3, characterized in that said charge pump type comparator (20) includes a couple (24,27) (25,28) (P 1 ) of inverters and AND gates , said output pulse/of said first frequency divider/is applied to one of said inverters (24) and AND gates (28), said output pulse (p 2 ) of said second frequency divider/ (27) (25) is applied to the other of said inverters/and AND gates/ (24,27) output signals of said inverters are connected to said AND gates (25,28), respectively and first and second current sources (41,42) for charging and discharging a capacitor (C p ) in response to output signals of said couple of AND gates (25,28).
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