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EP0169030A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processing circuit for calculating either a total sum or a total product of a series of data at a high speed

Assignee: NEC Corp
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Filing: 1985-07-11
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Granted: —
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Expires: 2005-07-11
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Abstract

Abstract In a data processing circuit for calculating a total sum of a succession of data in a pipeline fashion, an arithmetic unit (28) carries out an addition iteratively on the data to produce intermediate results of addition. Work registers (31, 32), equal in number to the number of the pipeline stages, successivelytem- porarily store the intermediate results. Specifying circuit (35) cyclically specifies the work registers as specified registers to store the intermediate results in the specified registers in the pipeline fashion. Selector (33) selects each of the work registers as a selected register to supply the arithmetic unit with the intermediate result stored in the selected register. When the arithmetic unit carries out the addition on all the data, contents of the work registers are added to each other by the use of the arithmetic unit to provide an ultimate result representative of the total sum.

Inventors

  • 👤 Kenji C/O Nec Corporation Hasegawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 10:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/509; G06F7/5095; G06F7/52; G06F7/523

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 74 words
A data processing circuit comprising calculating means (28) responsive to a succession of data for carrying out a predetermined calculation iteratively on the data of the succession to provide intermediate calculation results; a plurality of work registers (31, 32) for successively temporarily storing the calculation results; and administrating means (33, 35) for administrating the work registers to cyclically transfer the intermediate results among the work registers and the calculating means in a pipeline fashion.
Claim 2
Dependent Claim 74 words
A data processing circuit comprising calculating means (28) responsive to a succession of data for carrying out a predetermined calculation iteratively on the data of the succession to provide intermediate calculation results; a plurality of work registers (31, 32) for successively temporarily storing the calculation results; and administrating means (33, 35) for administrating the work registers to cyclically transfer the intermediate results among the work registers and the calculating means in a pipeline fashion.
Claim 3
Dependent Claim 100 words
A data processing circuit as claimed in claim 1, wherein the pipelining is carried out in a prescribed number of stages, characterised in that the administrating means comprises specifying means (35) for cyclically specifying the work registers (31, 32) as specified registers to store the intermediate results in the specified registers in the pipeline fashion, and selecting means (33) for selecting each of the work registers as a selected register to supply the calculating means (28) with the intermediate result stored in the selected register; and in that the number of work registers is equal to the said prescribed number.

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