Patent EP0167764A2 successfully refreshed from Google Patents.
EP0167764A2
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EP
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Dynamic ram cell
Assignee: International Business Machines Corp
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Filing: 1985-05-23
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Granted: —
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Expires: 2005-05-23
Abstract
Abstract A Dynamic Random Access Memory (DRAM) cell has a storage capacitor (3) disposed in a trench (5) formed in a semiconductor substrate (6). The substrate is heavily doped and forms the counterelectrode of the storage capacitor, and a heavily doped polycrystalline plug (4) disposed in the trench forms the other electrode. The DRAM cell includes an access transistor (8, 9, 10, 11) which is disposed adjacent the top of the storage capacitor, and source (8) of the access transistor is connected to the plug electrode (4).
Inventors
- 👤 Nicky Chau-Chun Lu
- 👤 Tak Hung Ning
- 👤 Lewis Madison Terman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 16:24
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/373
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
89 words
A dynamic random access memory cell comprising: a semiconductor substrate (6) at least a portion of which is highly conductive, a trench (5) in said substrate, a conductive element (4) disposed in said trench in insulated spaced relationship with said substrate, said conductive element and said highly conductive portion of the substrate being storage capacitor electrodes for the cell, and a field effect transistor (2) having source (8), drain (9) and gate (11) electrodes disposed adjacent to said conductive element, said source electrode being connected to said conductive element.
Claim 2
Dependent Claim
89 words
A dynamic random access memory cell comprising: a semiconductor substrate (6) at least a portion of which is highly conductive, a trench (5) in said substrate, a conductive element (4) disposed in said trench in insulated spaced relationship with said substrate, said conductive element and said highly conductive portion of the substrate being storage capacitor electrodes for the cell, and a field effect transistor (2) having source (8), drain (9) and gate (11) electrodes disposed adjacent to said conductive element, said source electrode being connected to said conductive element.
Claim 3
Dependent Claim
20 words
A dynamic random access memory cell according to Claim 1 wherein said field effect transistor is disposed over said trench.
Claim 4
Dependent Claim
28 words
A dynamic random access memory cell according to Claim 2 wherein said field effect transistor falls within the periphery of said trench at the surface of said substrate.
Claim 5
Dependent Claim
20 words
A dynamic random access memory cell according to an preceding claim wherein said conductive element is heavily doped polycrystalline silicon.
Claim 6
Dependent Claim
73 words
A dynamic random access memory cell as claimed in claim 1 in which said field effect transistor comprises a layer of semiconductor material having drain, source and channel regions therein disposed on an insulation layer (12), said source region having a portion which extends through a via hole in said insulation layer (12) and contacts the surface of said conductive element,and a gate electrode disposed in insulated spaced relationship over said channel region.
Claim 7
Dependent Claim
23 words
A dynamic random access memory cell according to claim 5 wherein said layer of semiconductor material is a layer of recrystallized polycrystalline silicon.
Claim 8
Dependent Claim
21 words
A dynamic random access memory cell according to claim 5 wherein said gate electrode is made of heavily doped polycrystalline silicon.
Claim 9
Dependent Claim
32 words
A dynamic random access memory cell according to claim 1 wherein a layer comprised of silicon dioxide and silicon nitride provides said insulated spaced relationship between said conductive element and said substrate.
Claim 10
Dependent Claim
55 words
A dynamic random access memory cell as claimed in claim 1 in which said substrate (104) includes a well region (105) of opposite conductivity type, said field effect transistor being formed in said well region and said conductive element (112) extending from the surface of said well through the well and further into said substrate.
Claim 11
Dependent Claim
40 words
A dynamic random access memory cell according to claim 9 wherein said substrate includes a heavily doped portion (111) and a lightly doped portion (108) disposed over said heavily doped portion, said well region being in said lightly doped portion.
Claim 12
Dependent Claim
32 words
A dynamic random access memory cell according to claim 9 including a region (114) of polycrystalline semiconductor material interconnecting the source electrode (106) of the field effect transistor and said conductive element.
Claim 13
Dependent Claim
103 words
A dynamic random access memory cell according to claim 9 in combination with a second cell oppositely arranged in the substrate having regard to its associated field effect transistor and conductive element, the gate electrode (115) of the first cell's field effect transistor being part of a first conductive line (WL1) which includes a portion of reduced width extending over the conductive element (112) of the second cell, and the gate electrode of the second cell's field effect transistor being part of a second conductive line (WL2) which includes a portion of reduced width extending over the conductive element of the first cell.
References Cited (Backward Citations)
No citation records indexed.
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