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EP0167275A2
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1985-05-30
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Granted: —
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Expires: 2005-05-30
Abstract
Abstract A semiconductor memory device includes an address change detection circuit (TR o . TR,...) and a pulse width control circuit (PWC). The pulse width control circuit (PWC) inhibits the passage of write enable signals (WE) having a short pulse width for a predetermined time period after a change of address has occurred. After the predetermined period has elapsed the operation of the pulse width control circuit (PWC) is overridden and thus the write cycle time is reduced.
Inventors
- 👤 Kazuhiro Toyoda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C8/00; G11C11/40; G11C7/00; G11C7/22; G11C8/18
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
86 words
A semiconductor memory device having a write signal generator including a pulse width control circuit (PWC) obtaining the logical product of a write signal (WE) and a delayed signal (SIG(P)) derived from it, and generating an internal write signal WE(INT) only when both are present simultaneously, characterised in that the write signal generator includes means (Tr 0' Tr l ,....Tr n ; G2) which enable the operation of the pulse width control circuit (PWC) only during a predetermined period after the detection of an address change.
Claim 2
Dependent Claim
86 words
A semiconductor memory device having a write signal generator including a pulse width control circuit (PWC) obtaining the logical product of a write signal (WE) and a delayed signal (SIG(P)) derived from it, and generating an internal write signal WE(INT) only when both are present simultaneously, characterised in that the write signal generator includes means (Tr 0' Tr l ,....Tr n ; G2) which enable the operation of the pulse width control circuit (PWC) only during a predetermined period after the detection of an address change.
Claim 3
Dependent Claim
99 words
A semiconductor memory device including a pulse width control circuit (PWC) for inhibiting the passage of write enable signals (WE) having the pulse width smaller than a predetermined pulse width, characterised in that the device also includes an address change detecting means (Tr 0 , Tr.1, ....Tr n ) for detecting a change of address of memory cells and delivering an output signal for a predetermined period of time upon the detection of a change of address, and in that the pulse width control means inhibits the passage of the write enable signals (WE) only during said predetermined period.
Claim 4
Dependent Claim
99 words
A semiconductor memory device including a pulse width control circuit (PWC) for inhibiting the passage of write enable signals (WE) having the pulse width smaller than a predetermined pulse width, characterised in that the device also includes an address change detecting means (Tr 0 , Tr.1, ....Tr n ) for detecting a change of address of memory cells and delivering an output signal for a predetermined period of time upon the detection of a change of address, and in that the pulse width control means inhibits the passage of the write enable signals (WE) only during said predetermined period.
Claim 5
Dependent Claim
96 words
A semiconductor memory device according to claim 1 or 2, wherein the pulse width control circuit (PWC) comprises: a delay element (Gl) for delaying the write enable signal (WE); a first gate circuit (G2) for controlling the passage of the delayed signal from the delay element (G1) in accordance with the output signal of the address change detecting means (Tr 0 , Tr l , ... Tr n ); and a second gate circuit (G2) for controlling the passage of the write enable signal in accordance with the output signal of the first gate circuit (G2).
Claim 6
Dependent Claim
25 words
A semiconductor memory device according to claim 1, 2 or 3, wherein the pulse width control circuit (PWC) is constituted by a negative logic circuit.
Claim 7
Dependent Claim
35 words
A semiconductor memory device according to claim 4, wherein the delay element is an inverter (G1), the first gate circuit is a NOR gate (G2), and the second gate circuit is an OR gate (G3).
Claim 8
Dependent Claim
27 words
A semiconductor memory device according to claim 1, 2 or 3, wherein the pulse width control circuit (PWC) is constituted by a positive logic circuit (Fgirure 11).
Claim 9
Dependent Claim
36 words
A semiconductor memory device according to claim 6, wherein the delay element is an inverter (G4), and the first gate circuit is a NAND gate (G5), and the second gate circuit is an AND gate (G6).
Claim 10
Dependent Claim
102 words
A semiconductor memory device according to claim 2 or any of claims 3 to 7 when dependent upon claim 2, wherein the address change detecting means comprises two-emitter transistors (Tr 0 , Tr 1 ,... Tr n ) whose collectors are connected to word lines (WL o , WL 1 ...) and whose bases are connected to word drivers (WD 0 , WD 1 ...) one of each two emitters being connected to current sources (I H ), and the other of each two emitters being commonly connected, the output (SIG(AD)) of the detecting means being taken out from the common junction.
Claim 11
Dependent Claim
35 words
A semiconductor memory device according to claim 8, wherein said address change detecting means further comprises a pulse width extension circuit (PWE) for extending the output signal (SIG(AD)) taken out from the common junction point.
References Cited (Backward Citations)
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