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Patent US3844825A successfully refreshed from Google Patents.
Patent EP0167061A2 successfully refreshed from Google Patents.
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EP0167061A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Vector processing computer

Assignee: Convex Computer Corp
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Filing: 1985-06-19
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Granted: —
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Expires: 2005-06-19
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Abstract

Abstract A vector processing computer (20) includes a memory control unit (22), main memory (99), a central processor (156). a service processing unit (42) and a plurality of input output processors (54, 68). The central processor (156) includes a physical cache unit (100), an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144), an odd pipe vector processing unit (148) and an even pipe vector processing unit (150). The computer (20) is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory (99), a physical cache unit (100) or a logical cache (326) through a source bus (114) where the elements are alternately loaded into the vector processing units (148, 150). The vector control unit (144) decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units (148, 150). Thus, the vector processing units (148. 150) essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus (114) to either the physical cache unit (100), the main memory (99), the logical cache (326) or to an input / output processor (54). In a further aspect of the computer (20) there is produced an entry microword from a store (350) for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store (376). This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer (20) there is included the logical data cache (326) which stores data at logical addresses such that the central processor (156) can store and retrieve data without the necessity of first making a translation from logical to physical address.

Inventors

  • 👤 Jeffrey H. Gruger
  • 👤 David M. Chastain
  • 👤 James R. Weatherford

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-04 16:58
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8061; G06F15/8069

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 146 words
A vector processing computer which includes a central processor and a memory wherein there are stored a plurality of vectors each having a plurality of elements, the computor comprising: a first vector processing unit within said central processor for executing vector instructions with said vectors, a second vector processing unit within said central processor for executing vector instructions with said vectors, a bus for conveying the elements of said vectors from said memory to said vector processing units, and a vector control unit within said central processor, said vector control unit connected to initiate and control said vector processing units and for directing the loading of said elements via said bus to said vector processing units wherein alternate ones of said elements are input to said first vector processing unit and the remaining alternate ones of said elements are input to said second vector processing unit.
Claim 2
Dependent Claim 146 words
A vector processing computer which includes a central processor and a memory wherein there are stored a plurality of vectors each having a plurality of elements, the computor comprising: a first vector processing unit within said central processor for executing vector instructions with said vectors, a second vector processing unit within said central processor for executing vector instructions with said vectors, a bus for conveying the elements of said vectors from said memory to said vector processing units, and a vector control unit within said central processor, said vector control unit connected to initiate and control said vector processing units and for directing the loading of said elements via said bus to said vector processing units wherein alternate ones of said elements are input to said first vector processing unit and the remaining alternate ones of said elements are input to said second vector processing unit.
Claim 3
Dependent Claim 19 words
A vector processing computer as recited in Claim 1 wherein said first and second vector processing units are identical.
Claim 4
Dependent Claim 45 words
A vector processing computer as recited in Claim 1 wherein odd ones of said elements conveyed through said bus are input to said first vector processing unit and even ones of said elements conveyed through said bus are input to said recorded vector processing unit.
Claim 5
Dependent Claim 28 words
A vector processing computer as recited in Claim 1 including a means for conveying resulting vectors produced by said vector processing units to said memory for storage therein.
Claim 6
Independent Claim 127 words
A method for operating with vectors in a vector processing computer which includes a central processor and a memory wherein the vector are stored in the memory and each vector comprises a plurality of elements, the method comprising the steps of: selecting one or more vectors stored in said memory for processing within said central processor, transmitting the elements of the selected vector from said memory through a bus which is connected to said first and second vector processing units, loading the elements transmitted through said bus into said vector processing units by loading alternate elements into said first vector processing unit and the remaining alternate elements into said second vector processing unit, and processing said vector elements loaded into said first and second vector processing units.
Claim 7
Independent Claim 127 words
A method for operating with vectors in a vector processing computer which includes a central processor and a memory wherein the vector are stored in the memory and each vector comprises a plurality of elements, the method comprising the steps of: selecting one or more vectors stored in said memory for processing within said central processor, transmitting the elements of the selected vector from said memory through a bus which is connected to said first and second vector processing units, loading the elements transmitted through said bus into said vector processing units by loading alternate elements into said first vector processing unit and the remaining alternate elements into said second vector processing unit, and processing said vector elements loaded into said first and second vector processing units.
Claim 8
Dependent Claim 23 words
The method recited in Claim 5 wherein said vector elements are transmitted from said memory sequentially according to the address for each element.
Claim 9
Dependent Claim 26 words
The method recited in Claim 5 wherein said vector elements are transmitted from said memory in a periodic but non-incremental order by address for each element.
Claim 10
Dependent Claim 24 words
The method recited in Claim 5 wherein said vector elements arc transmitted from said memory in a psuudo-randum order by address for each element.

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