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EP0166575A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

System for testing functional electronic circuits

Assignee: UTI Corp
•
Filing: 1985-06-20
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Granted: —
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Expires: 2005-06-20
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Abstract

Abstract A system (11) for enhancing the testability of functional electronic circuitry may be provided as a separate device or incorporated in circuits and includes serial or parallel control point input data capability applied through tri-statable output drivers (24) to input nodes of circuit elements of functional circuitry without interference with such circuitry during non-testing situations, and receivers (31) for observing resultant logic states at output nodes of functional circuitry being tested. The system comprises a control point section (12) having a decoder/demultiplexer (28) and a serializer (21), and a visibility point section (13) having a serializer (34) and an encoder/multiplexer (39).

Inventors

  • 👤 Jon L. Turino

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 14:06
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/2733

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 104 words
A system for testing functional electronic circuits, characterised by a control point section having a decoder/demultiplexer for receiving parallel control point input data and a serializer connected to receive serial input data, the output of said decoder/demultiplexer being adapted to apply signals to control points of the circuit under test, and a visibility point section adapted for connection to visibility point output nodes of the circuit under test and including a serializer for producing visibility point data in serial form and an encoder/multiplexer for producing visibility point data in parallel form, all in response to control point or other data for testing circuit operation.
Claim 2
Independent Claim 104 words
A system for testing functional electronic circuits, characterised by a control point section having a decoder/demultiplexer for receiving parallel control point input data and a serializer connected to receive serial input data, the output of said decoder/demultiplexer being adapted to apply signals to control points of the circuit under test, and a visibility point section adapted for connection to visibility point output nodes of the circuit under test and including a serializer for producing visibility point data in serial form and an encoder/multiplexer for producing visibility point data in parallel form, all in response to control point or other data for testing circuit operation.
Claim 3
Dependent Claim 49 words
A system as claimed in claim 1, further characterised by said control point section having a plurality of output drivers switchable into three separate states, and a drive terminal for receiving switching signals for actuating said output drivers to apply parallel control point data to the circuit under test.
Claim 4
Dependent Claim 33 words
A system as claimed in claim 1 or 2 further characterised by means for clocking the output of said control point serializer and means for clocking the output of said visibility point serializer.
Claim 5
Independent Claim 38 words
A system as claimed in any preceding claim, further characterised by at least one address unit for receiving addresses and applying said addresses to said control point decoder/demultiplexer and to said visibility point encoder/multiplexer for parallel data handling.

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