Digital data processing device with address allocation means

Claim 1

In a digital data processing device, provided with a plurality of assembled units, each of them including a predetermined number of circuits, to which addresses different from each other are allocated and which are assembled in the form of a unit, in which, depending on address assignment information coming from the central processing part (CPU), the circuits assigned by said address assignment information and said central processing part (CPU) transmit information to each other, the improvement wherein it comprises further: a reference address memory means (1) storing an inputted reference address by application of predetermined timing signals in each of said assembled units, successive addresses being allocated to said plurality of circuits in said assembled units, which are so arranged that the address used next to the last address in the assembled unit arranged in a preceeding stage among the plurality of them is allocated to the first circuit in the assembled unit in the succeeding stage; a circuit number setting device (2) for setting at least a value corresponding to the number of circuits included in a relevant assembled unit; a reference address operation means (3) for calculating and outputting the reference address of said assembled unit arranged in the stage next to said relevant assembled unit on the basis of the content of said reference address memory means (1) and that of said circuit number setting means (2); a timing signal generating means (6) for sending out a timing signal of predetermined timing to said assembled unit arranged in the succeeding stage at least after termination of the calculation; and an address judgement means (4) for judging if an address assignment information coming from the central processing device (CPU) is an information assigning said assembled unit or not, on the basis of the content of said reference address memory means and that of said circuit number setting means (2).