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Integrated circuit isolation structure and method of making

Assignee: International Business Machines Corp
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Filing: 1985-05-10
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Granted: —
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Expires: 2005-05-10
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Abstract

Abstract A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer (28, 30, 31) is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body (12). A epitaxial layer (40) extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation: where y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer (46) fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer (40). A second insulating layer (48) is located on the polycrystalline silicon layer (46) within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor layer (40) which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer (46) above the epitaxial layer (40) completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.

Inventors

  • 👤 Klaus Dietrich Beyer
  • 👤 Victor Joseph Silvestri

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 07:51
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10W10/00; H10W10/01; H10W10/041; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/025; Y10S148/026; Y10S148/05; Y10S148/085

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 106 words
Integrated circuit isolation structure comprising a pattern of substantially vertically sided trenches within a semiconductor body, a first insulating layer (28, 30, 31) upon the sidewalls of said trenches, and an epitaxial layer (40) within said trenches, characterized by said epitaxial layer (40) extending from the base of said trenches and filling said trenches up to between about 0.3 to 4.0 micrometers from the upper surface of said trenches, a polycrystalline silicon layer (46) over said the upper surfaces of said epitaxial layer (40), and a second insulating layer (48) on the said polycrystalline silicon layer (46) which isolates said pattern of trenches from the ambient.
Claim 2
Dependent Claim 106 words
Integrated circuit isolation structure comprising a pattern of substantially vertically sided trenches within a semiconductor body, a first insulating layer (28, 30, 31) upon the sidewalls of said trenches, and an epitaxial layer (40) within said trenches, characterized by said epitaxial layer (40) extending from the base of said trenches and filling said trenches up to between about 0.3 to 4.0 micrometers from the upper surface of said trenches, a polycrystalline silicon layer (46) over said the upper surfaces of said epitaxial layer (40), and a second insulating layer (48) on the said polycrystalline silicon layer (46) which isolates said pattern of trenches from the ambient.
Claim 3
Dependent Claim 41 words
The integrated circuit isolation structure as claimed in claim 1, characterized in that a nucleating layer (44) is located upon said sidewalls in the area where said polycrystalline layer (46) over said upper surfaces of said epitaxial layer (40) is present.
Claim 4
Dependent Claim 33 words
The integrated circuit isolation structure as claimed in claim 1 or 2, characterized in that said first insulating layer is composed of a silicon dioxide layer (28) and a silicon nitride layer (30).
Claim 5
Dependent Claim 43 words
The integrated circuit isolation structure as claimed in one of the claims 1 to 3, characterized in that the depth of said trenches is between about 3 to 10 micrometers, and the width of said trenches is between about 1 to 10 micrometers.
Claim 6
Dependent Claim 28 words
The integrated circuit isolation structure as claimed in claims 1 to 4, characterized in that said second insulating layer (48) is composed of a thermally grown silicon dioxide.
Claim 7
Dependent Claim 89 words
Method for forming the integrated circuit isolation structure in a monocrystalline silicon body as claimed in claims 1 to 5, characterized by providing a substantially vertically sided pattern of trenches having an insulating layer sidewall and monocrystalline silicon bottom, epitaxially growing monocrystalline silicon (40) in said trenches from said monocrystalline silicon bottom, ending said monocrystalline growth between about 0.3 to 4.0 micrometers from the top of said trenches, and depositing polycrystalline silicon (46) over the surface containing said trench and in said trenches until the said trenches are filled.
Claim 8
Dependent Claim 48 words
The method as claimed in claim 2, characterized in that a layer of nucleating material (44) is formed on the surfaces of the said insulating layer sidewall in the region and the upper surfaces of the said epitaxial silicon (40) where said polycrystalline silicon is to be formed.
Claim 9
Dependent Claim 17 words
The method as claimed in claim 7, characterized in that said nucleating layer (44) is polycrystalline silicon.
Claim 10
Dependent Claim 27 words
The method as claimed in claim 6 wherein the said polycrystalline silicon (46) is deposited using the same deposition system used for said epitaxially growing silicon (40).
Claim 11
Independent Claim 24 words
The method as claimed in claims 6 to 9, characterized in that said polycrystalline silicon layer (46) is removed in areas above said trenches.
Claim 12
Independent Claim 35 words
The method as claimed in claims 6 to 10, characterized in that the upper surfaces of said polycrystalline silicon layer (46) in said trenches are thermally oxidized to form a silicon dioxide cap (48) thereon.

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