Patent EP0165603A2 successfully refreshed from Google Patents.
EP0165603A2
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EP
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Resilient data processing bus system
Assignee: Bull HN Information Systems Inc
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Filing: 1985-06-19
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Granted: —
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Expires: 2005-06-19
Abstract
Abstract A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and checking apparatus for verifying that all of the parts of a request received from such unit over the bus are valid. When less than all of the parts of the request are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
Inventors
- 👤 George J. Barlow
- 👤 James W. Keeley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 19:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213; G06F11/00
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
170 words
A system including a plurality of units coupled in common to a system bus for transferring requests between said plurality of units during different bus cycles of operation, said system further including: means included in at least one of said plurality of units for generating requests on said bus, each request containing a number of different parts, said parts each containing a number of integrity bits for verifying when said request is validly received by another unit of said plurality of units during a bus cycle of operation; checking means included in said another unit for verifying that all of said number of different parts of said each request received by said another unit are valid; and, response means included in said another unit, said response means being coupled to said checking means and to said bus, said response means being conditioned by said checking means when less than all of said parts of said received request are valid, from generating any response on said bus to said one unit.
Claim 2
Independent Claim
170 words
A system including a plurality of units coupled in common to a system bus for transferring requests between said plurality of units during different bus cycles of operation, said system further including: means included in at least one of said plurality of units for generating requests on said bus, each request containing a number of different parts, said parts each containing a number of integrity bits for verifying when said request is validly received by another unit of said plurality of units during a bus cycle of operation; checking means included in said another unit for verifying that all of said number of different parts of said each request received by said another unit are valid; and, response means included in said another unit, said response means being coupled to said checking means and to said bus, said response means being conditioned by said checking means when less than all of said parts of said received request are valid, from generating any response on said bus to said one unit.
Claim 3
Dependent Claim
99 words
The system of claim 1 wherein said system further includes timeout means coupled to said system bus, said timeout means being operative in the absence of any response from said another unit to generate a predetermined signal on said bus after a predetermined period of time indicating that said another unit has not accepted said request and said one unit further including retry means coupled to said system bus, said retry means in response to said signal being operative to condition said generating means to retry said request on said system bus during a subsequent bus cycle of operation.
Claim 4
Dependent Claim
47 words
The system of claim 2 wherein said one unit further includes indicator means coupled to said retry means, said indicator means being operative in response to said predetermined signal to generate a first error signal signifying the occurrence of a first retry operation by said one unit.
Claim 5
Dependent Claim
55 words
The system of claim 3 wherein said one unit further includes error means coupled to said retry means, said error means being operative in response to a second occurrence of said predetermined signal to generate a second error signal signifying that said first retry operation was unsuccessful and that said request is to be aborted.
Claim 6
Dependent Claim
47 words
The system of claim 1 wherein said system bus includes a plurality of sections, each arranged for receiving at least one predetermined part including at least one of said number of integrity bits of each said request during each of a number of bus cycles of operation.
Claim 7
Dependent Claim
54 words
The system of claim 1 wherein said plurality of sections include a multibit address bus section, a multibit data bus section and a multibit command bus section for receiving an address, data and command bits including said number of integrity bits of each request during each of said number of bus cycles of operation.
Claim 8
Independent Claim
291 words
A system including a plurality of units of new and old designs coupled in common to a system bus for transferring requests between said plurality of units during different asynchronously generated bus cycles of operation, said system further including: first means included in at least a first unit of said plurality of units for generating requests on said bus, each request containing a number of different parts, said parts, each containing at least one integrity bit for verifying that said request is validly received by a second unit of said plurality of units during a bus cycle of operation; said system bus including a new parity line coupled only to each of said units of new design; second means included in said first unit for applying a predetermined signal to said new parity line which identifies to a second one of said plurality of units receiving said request that said request includes all integrity bits required for verifying that all of said number of parts of said request are valid; checking means included in each of said plurality of units, said checking means of each of said units of new design being coupled to said new parity line and operative in response to said predetermined signal to verify that all of said number of different parts of said request received by said unit are valid; and, response means included in each of said plurality of units, said response means being coupled to said checking means and to said bus, said response means of each of said units of said new design being conditioned by said checking means when less than all of said parts of said received request are valid from generating any response on said bus to said first unit.
Claim 9
Independent Claim
291 words
A system including a plurality of units of new and old designs coupled in common to a system bus for transferring requests between said plurality of units during different asynchronously generated bus cycles of operation, said system further including: first means included in at least a first unit of said plurality of units for generating requests on said bus, each request containing a number of different parts, said parts, each containing at least one integrity bit for verifying that said request is validly received by a second unit of said plurality of units during a bus cycle of operation; said system bus including a new parity line coupled only to each of said units of new design; second means included in said first unit for applying a predetermined signal to said new parity line which identifies to a second one of said plurality of units receiving said request that said request includes all integrity bits required for verifying that all of said number of parts of said request are valid; checking means included in each of said plurality of units, said checking means of each of said units of new design being coupled to said new parity line and operative in response to said predetermined signal to verify that all of said number of different parts of said request received by said unit are valid; and, response means included in each of said plurality of units, said response means being coupled to said checking means and to said bus, said response means of each of said units of said new design being conditioned by said checking means when less than all of said parts of said received request are valid from generating any response on said bus to said first unit.
Claim 10
Dependent Claim
105 words
The system of claim 7 wherein said checking means of each unit of said new design is operative in the absence of said predetermined signal to perform a checking operation on less than all of said parts of said received request and said response means of said each unit of said new design being conditioned by said checking means as a result of such checking operation to generate a response to one of said units of said old design which transmitted said received request, which is the same as would have been generated in the system, which included only said units of said old design.
Claim 11
Dependent Claim
50 words
The system of claim 7 wherein said response means of each unit of said new design is conditioned by said checking means when all of said parts of said received request are valid to generate a predetermined response to said first unit signalling that said request has been validly received.
Claim 12
Dependent Claim
75 words
The system of claim 9 wherein each of said units of said new design include connector means for applying said number of said integrity bits to said bus in a predetermined manner for enabling each of said units of said old design coupled to said bus to disregard said integrity bits and perform a check only those parts of said received request verified in said system designed to include said units of said old design.
Claim 13
Dependent Claim
99 words
The system of claim 7 wherein said system further includes timeout means coupled to said system bus, said timeout means being operative in the absence of any response from said another unit to generate a predetermined signal on said bus after a predetermined period of time indicating that said another unit has not accepted said request and said one unit further including retry means coupled to said system bus, said retry means in response to said signal being operative to condition said generating means to retry said request on said system bus during a subsequent bus cycle of operation.
Claim 14
Dependent Claim
47 words
The system of claim 8 wherein said one unit further includes indicator means coupled to said retry means, said indicator means being operative in response to said predetermined signal to generate a first error signal signifying the occurrence of a first retry operation by said one unit.
Claim 15
Dependent Claim
55 words
The system of claim 9 wherein said one unit further includes error means coupled to said retry means, said error means being operative in response to a second occurrence of said predetermined signal to generate a second error signal signifying that said first retry operation was unsuccessful and that said request is to be aborted.
Claim 16
Dependent Claim
48 words
The system of claim 7 wherein said system bus includes a plurality of sections, each arranged for receiving at least one predetermined part including at least one of said number of integrity bits of each of said request during each of a number of bus cycles of operation.
Claim 17
Dependent Claim
54 words
The system of claim 7 wherein said plurality of sections include a multibit address bus section, a multibit data bus section and a multibit command bus section for receiving an address, data and command bits including said number of integrity bits of each request during each of said number of bus cycles of operation.
Claim 18
Dependent Claim
72 words
The system of claim 8 wherein said checking means of each unit of said new design further includes transfer means coupled to said new parity line and to said system bus, said transfer means being operative to transfer to internal paths within said each unit, integrity bits generated by said checking means for those parts of said request received from said unit of said old design which did not contain integrity bits.
Claim 19
Independent Claim
190 words
A method of constructing a resilient bus system for transferring requests during different bus cycles of operation between a plurality of data handling units coupled in common to said bus system, said method comprising the steps of: (a) including in at least one of said data handling units, means for generating requests on said bus system in which each request contains a number of different parts, said parts each containing a number of integrity bits for verifying when said request is validly received by another unit of said plurality of units during a bus cycle of operation; (b) including in at least another one of said data handling units, checking means for verifying that all of said number of different parts of said each request received by said another data handling unit are valid; and, (c) including in said another one of said data handling units, response means which connects to said checking means and to said bus system and only generates a response on said bus when all of said parts of said request are signalled by said checking means as being valid thereby preventing acceptance of invalid requests.
Claim 20
Independent Claim
190 words
A method of constructing a resilient bus system for transferring requests during different bus cycles of operation between a plurality of data handling units coupled in common to said bus system, said method comprising the steps of: (a) including in at least one of said data handling units, means for generating requests on said bus system in which each request contains a number of different parts, said parts each containing a number of integrity bits for verifying when said request is validly received by another unit of said plurality of units during a bus cycle of operation; (b) including in at least another one of said data handling units, checking means for verifying that all of said number of different parts of said each request received by said another data handling unit are valid; and, (c) including in said another one of said data handling units, response means which connects to said checking means and to said bus system and only generates a response on said bus when all of said parts of said request are signalled by said checking means as being valid thereby preventing acceptance of invalid requests.
Claim 21
Dependent Claim
65 words
The method of claim 17 wherein said method further includes the steps of: (d) connecting timeout means to said bus system for signalling the unit which transmitted a request when the intended receiving unit had not accepted the request because it was invalid; and, (e) including within such transmitting unit, retry means coupled to said bus system for retrying the request on said bus system.
Claim 22
Dependent Claim
55 words
The method of claim 17 wherein said method further includes the steps of: adding a new parity line to said bus system when said data handling units include units of old and new designs; and, connecting the new parity line only as an input to the checking means of each unit of a new design.
Claim 23
Dependent Claim
21 words
The method of claim 17 wherein said one and said another one of said data handling units are the same unit.
References Cited (Backward Citations)
No citation records indexed.
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