Input/output bus for computer

Claim 2

An input/output bus system for providing communication of data blocks (164) between a computer (12) and one or more peripheral units (18) via a bus (14) wherein a bus arbiter (38) selectively grants use of the bus (14) to one of the peripheral units (18), the bus (14) includes a plurality of address/datalines (58) connected in parallel to the computer (12) and the peripheral units (18, 20) for bidirectional transmission of data through the lines (58), the bus arbiter (38) grants use of the lines (58) in the absence of a conflict and on a predetermined priority basis when there is a conflict for use of the address/data lines (58) by the computer (12) and the peripheral units (18, 20), a request line (42) and grant line (44) is provided for each of the peripheral units (18) for connection to the bus arbiter (38), and a plurality of handshake lines (60) connect the computer (12) to the peripheral units (18, 20) for controlling transmission of addresses and data, characterized by, a plurality of circuit means (134) respectively within each of said peripheral units (18, 20) for generating a header parcel (146) for transmission through said address/data lines (58) to said computer (12), said header parcel (146) comprising an address (148) for a first one of a plurality of data units which comprise a data block (164) to be transferred between said computer (12) and one of said peripheral units (18, 20), a count (152) indicating the size of said data block (164) and a command code (150) for indicating a read from or write to said computer (12), for said data block (164), circuit means (100) within each of said peripheral units (18, 20) and connected to said address/data lines (58) for transmitting said header parcel (146) from each of said peripheral units (18, 20) via said address/data lines (58) to said computer (12), circuit means (174) within said computer (12) for generating a sequence of addresses derived from said address included in said header parcel (146), said sequence of addresses corresponding to said units of said data block (164), storage means (104, 188, 192) within each of said peripheral units (18, 20) and said computer (12) for storing said data units therein, control circuit means (92) within each of said peripheral units (18, 20) and connected to control said address/data lines (58) for transferring said data units of said data block (164) via said address/data lines (58) between the storage means (188,192) in said computer (12) and the storage means (104) in said peripheral units (18, 20), circuit means (124) within each of said peripheral units (18, 20) for maintaining a count of the number of the units of said data block (164) transmitting between said computer (12) and said peripheral unit (18) following transmittal of said header parcel (146), and said circuit means (134) for generating a header parcel (146) is connected to receive said count for producing a new header parcel (146) when the transfer of said data block (164) has been terminated before completion, said new header parcel (146) including a new address derived from the address for said data block (164) and said count, said count for indicating the size of the remainder of the data block (164) and said command code, said new header parcel (146) for transmission from the generating peripheral unit (18) to said computer (12) to complete the transfer of said data block (164).