Patent EP0165106A2 successfully refreshed from Google Patents.
EP0165106A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1985-05-03
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Granted: —
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Expires: 2005-05-03
Abstract
Abstract A semiconductor memory device including at least two groups, each of said groups including a plurality of memory cell array blocks (CLAO, CLA1, ...). The number of the memory cell array blocks which are activated in one group is made different from the number of memory cell array blocks which is activated in another group by providing a sequential circuit (S1), thus reducing the maximum power consumption.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Tomio Nakano
- 👤 Kimiaki Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:05
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/409; G11C11/4096; G11C11/4097
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
266 words
A semiconductor memory device comprising: at least two groups each including a plurality of memory cell array blocks; included in each of said memory cell array blocks, a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells each being connected between one of the-bit lines comprising said bit line pairs and one of said word lines; switching means connected between bit line pairs included in two adjoining blocks of said plurality of memory cell array blocks for splitting or connecting the two adjoining blocks; a column decoder operatively connected to said bit line pairs for selecting a bit line pair to read data from a selected memory cell in one of said groups; a word decoder for simultaneously selecting a word line in one of the memory cell array blocks of one group and a word line in one of the memory cell array blocks in the other group and for selecting said word lines in such a way that the distance between said column decoder and the memory cell array block including said selected word line of said one group is different from the distance between said column decoder and the memory cell array block including said selected word line of said other group; and a switching control circuit for controlling said switching means so as to selectively drive the bit line pairs included in the memory cell array block including said selected word line and in another memory cell array block located between the memory cell array block including said selected word line and said column decoder.
Claim 2
Dependent Claim
266 words
A semiconductor memory device comprising: at least two groups each including a plurality of memory cell array blocks; included in each of said memory cell array blocks, a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells each being connected between one of the-bit lines comprising said bit line pairs and one of said word lines; switching means connected between bit line pairs included in two adjoining blocks of said plurality of memory cell array blocks for splitting or connecting the two adjoining blocks; a column decoder operatively connected to said bit line pairs for selecting a bit line pair to read data from a selected memory cell in one of said groups; a word decoder for simultaneously selecting a word line in one of the memory cell array blocks of one group and a word line in one of the memory cell array blocks in the other group and for selecting said word lines in such a way that the distance between said column decoder and the memory cell array block including said selected word line of said one group is different from the distance between said column decoder and the memory cell array block including said selected word line of said other group; and a switching control circuit for controlling said switching means so as to selectively drive the bit line pairs included in the memory cell array block including said selected word line and in another memory cell array block located between the memory cell array block including said selected word line and said column decoder.
Claim 3
Dependent Claim
76 words
A semiconductor memory device as set forth in claim 1, further comprising a plurality of sense amplifiers each for amplifying the potential difference between a selected bit line pair, said switching control circuit comprising a sequential circuit, operatively connected to said sense amplifiers, for controlling said sense amplifiers in such a way that the number of activated sense amplifiers in said one group is different from the number of activated sense amplifiers in said other group.
Claim 4
Dependent Claim
40 words
A semiconductor memory device as set forth in claim 2, wherein said switching means comprises a plurality of groups of transfer gate transistors, each group of said transfer gate transistors being connected between adjoining two of said bit line pairs.
Claim 5
Dependent Claim
103 words
A semiconductor memory device as set forth in claim 3, wherein said switching control circuit further comprises a selection circuit operatively connected to said plurality of groups of transfer gate transistors, for controlling said transfer gate transistors in such a way that, in response to a part of said input address signals, the number of groups of said transfer gate transistors being opened by said selection circuit in said one group of memory cell array blocks is different from the number of groups of said transfer gate transistors being opened by said selection circuit in said other group of memory cell array blocks.
Claim 6
Dependent Claim
146 words
A semiconductor memory device as set forth in claim 1, further comprising a plurality of sense amplifiers each for amplifying the potential difference between a selected bit line pair, wherein: said switching control circuit comprises a sequential circuit; said switching means comprises a plurality of groups of transfer gate transistors, each group of said transfer gate transistors being connected between one of said memory cell array blocks and one of said sense amplifiers; and said sequential circuit is operatively connected to said transfer gate transistors so as to control in such a way that the number of groups of said transfer gate transistors being opened by said sequential circuit in said one group of memory cell array blocks is different from the number of groups of said transfer gate transistors being opened by said sequential circuit in said other group of memory cell array biocks .
References Cited (Backward Citations)
No citation records indexed.
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