Patent EP0164673A2 successfully refreshed from Google Patents.
EP0164673A2
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Activity trace collection mechanism for peripheral devices in computer systems
Assignee: International Business Machines Corp
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Filing: 1985-06-03
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Granted: —
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Expires: 2005-06-03
Abstract
Abstract A trace collection mechanism for recording accesses to a peripheral device (12) having an I/O cache memory (20), comprises a clock (30) and control means (16). At each access of the memory, the beginning and ending times of the access are stored in a part (28) of the cache memory, together with parameters of the access, such as address and length of accessed data and the type of access. A set of collected data can be analyzed for the operation of both the peripheral device and the central processing program.
Inventors
- 👤 Gerald A. Marazas
- 👤 Jerry Duane Dixon
- 👤 Gerald Ulrich Merckel
- 👤 Andrew Boyce Mcneill
- 👤 Mahendra M. Bhansali
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 15:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/3485
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
110 words
In a controller (14) which couples a peripheral device (12) to a data processor, an activity trace collection mechanism comprising a storage mechanism (28) for storing information relating to the activity of said peripheral device, clock means (30) and a trace control mechanism (16) coupled to the storage mechanism (28) and the clock means (30) and operative during the normal operation of the controller (14) and peripheral device (12) for storing in said storage mechanism (28) the starting and ending times of each peripheral device operation and at least one other parameter defining the nature of each said peripheral device operation, said times being derived from said clock means (30).
Claim 2
Dependent Claim
110 words
In a controller (14) which couples a peripheral device (12) to a data processor, an activity trace collection mechanism comprising a storage mechanism (28) for storing information relating to the activity of said peripheral device, clock means (30) and a trace control mechanism (16) coupled to the storage mechanism (28) and the clock means (30) and operative during the normal operation of the controller (14) and peripheral device (12) for storing in said storage mechanism (28) the starting and ending times of each peripheral device operation and at least one other parameter defining the nature of each said peripheral device operation, said times being derived from said clock means (30).
Claim 3
Dependent Claim
43 words
A trace collection mechanism as recited in claim 1, wherein said peripheral device (12) includes a direct access storage device and said trace control mechanism (16) stores at least two parameters defining the limits of data accessed in said direct access storage device.
Claim 4
Dependent Claim
30 words
A trace collection mechanism as recited in claim 1 or 2, further comprising an I/O cache memory (20)for serving as intermediate storage between said peripheral device (12) and said processor.
Claim 5
Dependent Claim
52 words
A trace . collection mechanism as recited in claim 3 wherein said storage mechanism (28) and said cache memory (20) occupy a common memory device and said trace control mechanism (16) further comprises means for dynamically allocating storage on said memory device between said storage mechanism (28) and said cache memory (20).
Claim 6
Dependent Claim
46 words
A trace collection mechanism as recited in any previous claim, wherein said trace control mechanism (18) further comprises means for analyzing the operation of said data processor from said times and said parameters stored in said storage mechanism (28) for a plurality of peripheral device operations.
Claim 7
Dependent Claim
60 words
A trace collection mechanism as recited in claim 5, wherein said analyzing means include means for determining the elapsed time between the starting time and the ending time of a plurality of peripheral device operations, summing said elapsed times, and comparing said summed elapsed times to a total elapsed time during which said starting and ending times are being stored.
Claim 8
Dependent Claim
50 words
A trace collection mechanism as recited in claim 6, wherein said analyzing means includes means for determining the elapsed time between the ending time of a peripheral device operation requested by a task in said processor and the starting time of the next peripheral device operation from the same task.
Claim 9
Dependent Claim
31 words
A trace collection mechanism as recited in claim 7, wherein said determining means further determines which of said elapsed times exceed a limit statistically determined from a plurality of elapsed times.
Claim 10
Dependent Claim
25 words
A trace collection mechanism as recited in claim 5, wherein said trace control mechanism (16) and said analyzing means are both included in a microprocessor.
References Cited (Backward Citations)
No citation records indexed.
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