PCM coder/decoder with two-wire/four-wire conversion

Claim 2

A PCM coder and decoder comprising: a first circuit (7...9) which decodes a first PCM'signal into a first analogue signal; a second circuit (2...4) which codes a second analogue signal into a second PCM signal; and a balancing circuit (11...14) which is interposed between said first circuit (7...9) and said second circuit (2...4) in order to eliminate a signal produced when the output of said first circuit (7...9) returns to said second circuit (2...4); said balancing circuit including an analogue balancing circuit (13, 14) which subtracts the analogue signal of said first circuit (7...9) from the analogue signal of said second circuit (2...4) and whose characteristics are independent of frequencies, and a digital balancing circuit (11, 12) which subtracts the digital signal of said first circuit (7...9) from the digital-signal of said second circuit (2...4).

Claim 3

A PCM coder and decoder according to claim 1, wherein said first circuit is constructed of a first digital filter (7) for band limitation, a D/A converter (8) and a post-filter (9) which are connected in cascade in this order from an input side (6); said second circuit is constructed of a pre-filter (2), an A/D converter (3) and a second digital filter (4) which are connected in cascade in this order from an input side (1); 'said analogue balancing circuit is constructed of an amplifier (13; Fig. 3), whose input is an output of said post-filter (9), and a first operating unit (14) which subtracts an output of said amplifier (13) from the input of said second circuit (2...4) and which applies the subtracted signal to an input of said pre-filter (2); and said digital balancing circuit is constructed of a third digital filter (11) whose input is an output of said first digital filter (7), and a second operating unit (12) which subtracts an output of said third digital filter (11) from an output of said A/D converter (3) and which applies the subtracted signal to said second digital filter (4).

Claim 4

A PCM coder and decoder according to claim 2, further comprising an expandor (22) which converts an input compressed PC M signal into a linear PCM signal at an input side (6) of said first digital filter (7), and a compressor (21) which converts a linear _PCM signal into a µ-law compressed PCM signal.

Claim 5

A PCM coder and decoder according to claim 2, further comprising: an expandor (22) which converts a compressed input PCM signal of the first PCM signal into a linear PCM signal applied to the input terminal (6) of said first digital filter ( 7 ), and a compressor (21) which converts an output signal of said second digital filter (4) into a compressed PCM signal of the second PCM signal.

Claim 6

A PCM coder and decoder according to any of claims 2 to _4, wherein said amplifier (13) is so constructed that its gain can be set selectively in correspondence with a circuit constant of an outer circuit (15...17) which is connected to an output terminal (10) of said post-filter (9) and an input terminal (1) of said second circuit (2...4).

Claim 7

A PCM coder and decoder according to claim 5, wherein said outer circuit comprises a first amplifier (16), an impedance circuit (17) and a second amplifier (15) which are serially connected in this order between said output terminal (10) of said post-filter (9) and a terminal of said second operating unit to be supplied with the first analogue signal, and a telephone two-wire line (18) which is connected to a node between said impedance circuit (17) and an input of said second-amplifier (15); and wherein the circuit constant is either of gains of said first and second amplifiers (15, 16) and an impedance of said two-wire line (18).

Claim 8

A PCM coder and decoder according to claim 1, wherein said first circuit is constructed of a first digital filter (7-P) which converts the first PCM signal into a signal having a sampling frequency higher than that of the former signal, a second digital.-filter (7-S) which converts the output of said first digital filter (7-P) into a signal having a sampling frequency higher than that of the output of said first digital filter (7-P), a D/A converter (8) which converts the output of said second digital filter (7-S) into an analogue signal, and a post-filter (9); all the aforementioned constituents (7-P, 7-S, 8, 9) being connected in cascade in this order from an input side (6), said second circuit is constructed of an analogue pre-filter (2), an A/D converter (3), a third digital filter (4-P) which changes an output of said A/D converter (3) into a digital signal having a sampling frequency lower than that of the output, an operating unit (12), and a fourth digital filter (4-S) which changes an output of said operating unit (12) into a digital signal having a sampling frequency lower than that of the output of said third digital filter (4-P), all the aforementioned constituents (2, 3, 4-P, 4-S) being connected in cascade in this order from an input side (1), said digital balancing circuit (11) is connected between the output of said first digital,filter (7-P) and said operating unit (12), said operating unit (12) is a circuit which subtracts the output of said digital circuit from the output of said third digital filter (4-P), and said analogue balancing circuit (13) is connected between an output terminal of said post-filter (9) and an input terminal of said pre-filter (2).

Claim 9

A PCM coder and decoder according to claim 7, wherein the sampling frequency f 1 of the output of said third digital filter (4-P) and the sampling frequency f 3 of the output of said first digital filter (7-P) are at an integral ratio, and wherein a sum T d of delay times of said second digital filter (7-S), said D/A converter (8), said post-filter (9), said pre-filter (2), said A/D converter (3) and said third digital filter (4-D) is set so as to become equal to where max(f 1 f 2 ) denotes a maximum number of f and f 2' and n an integer.

Claim 10

A PCM coder and decoder according to claim 7 or 8, further comprising: first digital delay means (24) interposed between the output terminal of said first digital filter (7-P) and the input of said operating unit (12), and second digital delay means (23) interposed between the output of said second digital filter (7-S) and an input terminal of said D/A converter (8).

Claim 11

A PCM coder and decoder according to any of claims 7 to 9, further comprising: an expandor (22) which converts a compressed input PCM signal of the first PCM signal into a linear PCM signal applied to the input terminal (6) of said first digital filter (7-P), and a compressor (21) which converts an output signal of said fourth digital filter (4-S) into a compressed PC M signal of the second PCM signal.