Patent EP0162969A1 successfully refreshed from Google Patents.
EP0162969A1
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EP
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Switching circuits and matrix device using same
Assignee: Nokia Bell NV
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Filing: 1984-05-30
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Granted: —
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Expires: 2004-05-30
Abstract
Abstract The invention relates to switching circuits and matrix device using same and having the form of a flat panel comprising a control device and a smectic liquid crystal display including pixels arranged in a coordinate matrix of 400 rows and 720 columns. The control device includes several driver units located along the four sides of the rectangular matrix and serially interconnected along each side so as to constitute bidirectional shift registers for serial control data and information. Each driver unit controls 30 odd or 30 even numbered lines (rows or columns) and is able to apply to these lines for a predetermined duration DC voltages equal to either -150 Volts, -30 Volts, 0 Volt, +30 Volts or +150 Volts in function of these data and information.
Inventors
- 👤 Guido Petrus Theophiel Constant Remmerie
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 22:45
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3674; G09G3/3681; G09G3/3622; G09G3/3685; G09G3/3692; G09G2310/00; G09G2310/02; G09G2310/0264; G09G2310/0283
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
162 words
Matrix device (FPD) with a coordinate matrix (LC D ) and an associated control device, said coordinate matrix including a plurality of series of crossing electrical lines (rows, columns) defining crosspoints, said control device including a plurality of driver units (FPDR) arranged along different sides of said coordinate matrix and having line output terminals (OUTl/30) coupled to distinct ones of the lines of at least one of said series, and said control device including also an input signal source coupled to said driver units and adapted to supply input signals (DATALC/R, DATARC/R, CLKC/R, FREQC/R, ENC/R, SELC/R) to said driver units, characterized in that each of said driver units (FPDR) includes a plurality of driver circuits (LD, HVD) each having one of said line output terminals (OUT1/30) and interconnected so as to form a shift register, shift control means (CKC) to shift said input signals (DATALC/R, DATARC/R) through said shift register, and direction control means (RLC) for controlling the direction of said shift.
Claim 2
Dependent Claim
162 words
Matrix device (FPD) with a coordinate matrix (LC D ) and an associated control device, said coordinate matrix including a plurality of series of crossing electrical lines (rows, columns) defining crosspoints, said control device including a plurality of driver units (FPDR) arranged along different sides of said coordinate matrix and having line output terminals (OUTl/30) coupled to distinct ones of the lines of at least one of said series, and said control device including also an input signal source coupled to said driver units and adapted to supply input signals (DATALC/R, DATARC/R, CLKC/R, FREQC/R, ENC/R, SELC/R) to said driver units, characterized in that each of said driver units (FPDR) includes a plurality of driver circuits (LD, HVD) each having one of said line output terminals (OUT1/30) and interconnected so as to form a shift register, shift control means (CKC) to shift said input signals (DATALC/R, DATARC/R) through said shift register, and direction control means (RLC) for controlling the direction of said shift.
Claim 3
Dependent Claim
44 words
Matrix device according to claim 1, characterized in that said input signals (DATALC/R, DATARC/R, CLKC/R, FREQC/R, E NC/R, SELC/R) for said one series of lines being fed from said input signal source to a same side of sad matrix device (FPD) through connector terminals.
Claim 4
Dependent Claim
38 words
Matrix device according to claim 1, characterized in that said line output terminals (OUT1/30) coupled to two immediately adjacent lines of at least one of said series are connected at different sides of said coordinate matrix (LCD) respectively.
Claim 5
Dependent Claim
53 words
Matrix device according to claim 1, characterized in that said matrix device is a flat panel (FP D ) carrying a smectic liquid crystal flat panel display (LCD) which constitutes said coordinate matrix, and said driver units (FPDR) which are disposed around said display, cells of said display being located at said crosspoints.
Claim 6
Dependent Claim
54 words
Matrix device according to claim 1, characterized in that each of said driver circuits (LD, HVD) has logical means (LDl/30) including a signal switching circuit (PG1/5, INV16/18) controlled by said direction control means (RLC) and enabling complementary couplings between first (AI) and second (AO) terminals and, alternatively between third (BI) and fourth (BO) terminals.
Claim 7
Dependent Claim
78 words
Signal switching circuit (PGl/5, INV16/18) enabling controlled complementary couplings between first (AI) and second (AO) terminals and, alternatively between third (BI) and fourth (BO) terminals, characterized in that said second (AO) and fourth (BO) terminals are interconnected and coupled through a signal memory circuit (INV16, INV18, PG5) to the common terminal of two gates (PG1/2) controlled so as to be in complementary conductive states and whose other terminals-are respectively coupled to said first (AI) and third (BI) terminals.
Claim 8
Dependent Claim
78 words
Signal switching circuit (PGl/5, INV16/18) enabling controlled complementary couplings between first (AI) and second (AO) terminals and, alternatively between third (BI) and fourth (BO) terminals, characterized in that said second (AO) and fourth (BO) terminals are interconnected and coupled through a signal memory circuit (INV16, INV18, PG5) to the common terminal of two gates (PG1/2) controlled so as to be in complementary conductive states and whose other terminals-are respectively coupled to said first (AI) and third (BI) terminals.
Claim 9
Dependent Claim
41 words
Plurality of signal switching circuits as in claim 5, characterized in that said circuits are cascaded with the first (AI) and fourth (BO) terminals of one circuit respectively coupled to the second (AO) and third (BI) terminals of the next circuit.
Claim 10
Dependent Claim
38 words
Plurality of signal switching circuits as in claim 7, characterized in that the two terminals (AI, BO; AO, BI) at an end of said cascade are coupled through a controlled interface circuit (ICl/10) to a bidirectional line (BP).
Claim 11
Dependent Claim
112 words
Plurality of signal switching circuits as in claim 8 , characterized in that said controlled interface circuit ( I Cl/10) includes first means (NAND2, N OR 4, PM2, NM2) to regenerate and allow transmission of signals between said bidirectional line (BP) and one (AI; BI) of said two terminals (AI, B O; A O , BI) while transmission between the other (AO; BO) of these terminals and said bidirectional line is inhibited, and includes second means (INV13/15, NAND1, NOR3, PM1, NM1), to regenerate and allow transmission of signals between said other terminal (AO; BO) and said bidirectional line while transmission between said one terminal (AI; BI) and said bidirectional line is inhibited.
Claim 12
Dependent Claim
24 words
1 0 . Matrix device according to claim 5, characterized in that said signal switching circuit (PGl/5, INV16/18) is realized as per claim 6.
Claim 13
Dependent Claim
39 words
Matrix device according to claim 10, characterized in that said shift register formed by said driver circuits ( LD , HVD ) is realized by the cascade connection of the signal switching circuits (PGl/5, INV16/18) as per claim 7.
Claim 14
Dependent Claim
76 words
Matrix device according to claim 11, characterized in that each of said driver units (FPDR) has a plurality of control terminals (Il/5, Ol/5) to which said input signals (DATALC/R, DATRC/R, CLKC/R, FREQC/R, ENC/R,SELC/R) may be applied, and among which at least one is coupled to a controlled interface circuit (ICl/10) as per any of the claims 8 or 9 via said bidirectional line (BP), said interface circuit being controlled by said direction control means (RLC) .
Claim 15
Dependent Claim
36 words
Matrix device according to claim 12, characterized in that a plurality of driver units (FPDR) connected in series via said control terminals (Il/5, 01/5) are located along at least one side of said coordinate matrix (LCD).
Claim 16
Dependent Claim
112 words
Matrix device according to claim 10, characterized in that said logical means (LDl/30) further include combination means (PG6/7, XNR, NAND3, ANDl/3, INV19/22) coupled to said signal memory circuit (INV16, INV18, PG5) and adapted to translate said input signals (DATALC/R, DATARC/R , CLKC/R, FREQC/R, ENC/R, SELC/R) into a number of codes comprising a plurality of elements (IN1/3) controlling distinct one of a like plurality of circuits (HV1/3) forming a switching circuit (HVD) also included in said driver circuit (LD, HVD) and having said one line output terminal (OUT1/30) to which said output circuits are able to apply output signals (CSC, CC, CNC; RSC, RNSC, STROBE) defining the electrical state of the coupled line.
Claim 17
Dependent Claim
43 words
Matrix device according to claim 14, characterized in that said combination means (PG6/7, XNR, NAND3, ANDl/3, INV19/22) are provided with latching means (PG7, INV20/21) for latching some of said input signals (DATALC/R, DATARC/R) under the control of other of said input signals (ENC/R).
Claim 18
Dependent Claim
90 words
Switching circuit (HVD) able to selectively couple one out of at least three voltages at respective input terminals (+Vl, -V2, OV) to a common output terminal (OUT), characterized in that first (HVl) and second (HV2) circuits coupling respectively the first (+V1) and the second (-V2) input terminals to said common output terminal (OUT) include at least one DMOS switch device (NM4), and that at least one third circuit (HV3) coupling the third input terminal (OV) to said common output terminal includes two DMOS switch devices (NM7/8) coupled in series opposition.
Claim 19
Dependent Claim
90 words
Switching circuit (HVD) able to selectively couple one out of at least three voltages at respective input terminals (+Vl, -V2, OV) to a common output terminal (OUT), characterized in that first (HVl) and second (HV2) circuits coupling respectively the first (+V1) and the second (-V2) input terminals to said common output terminal (OUT) include at least one DMOS switch device (NM4), and that at least one third circuit (HV3) coupling the third input terminal (OV) to said common output terminal includes two DMOS switch devices (NM7/8) coupled in series opposition.
Claim 20
Dependent Claim
44 words
Switching circuit according to claim 16, characterized in that each of said circuits (HV1/3) further includes operating means (R8, NM3; Rll, NM6) associated to the respective DMOS switch device(s) (NM4; NM7/8) and able to open said DMOS switch device(s) more rapidly than closing it/them.
Claim 21
Dependent Claim
49 words
Switching circuit according to claim 16, characterized in that said circuits (HV1/3) are interconnected (Tl, T2) and coupled to logical means (LDl/30) controlled by input signals (FREQC/R, SELC/R, ENC/R) and able to generate a number of codes comprising three elements (IN1/3) each controlling a distinct one of said circuits.
Claim 22
Dependent Claim
70 words
Switching circuit according to claims 17 and 18, characterized in that each of said circuits (HV1/3) further includes a level translator (R5/6, P1; R9/10, P2) including an active device (Pl; P2) coupled between said logical means (LD) and said operating means (R8, NM3; Rll, NM6), and adapted to transform, together with said operating means, said elements (INl/3) of said codes into control signals for said DMOS switch devices (NM4; NM7/8).
Claim 23
Dependent Claim
72 words
2 0 . Switching circuit according to claim 19, characterized in that current flow through said DMOS switch devices (NM4; NM7/8), said operating means (R8, NM3; Rll, NM6) and said active devices (Pl; P2) of said level translators (R5/6, Pl; R9/10, P2) is inhibited when said three elements (INl/3) of said codes are such that the voltage at the third input terminal (OV) is applied to said common output terminal (OUT) .
Claim 24
Dependent Claim
97 words
Switching circuit according to claim 19, characterized in that said first (HV1) and said second (HV2) circuits are identical and have their level translator (R5/6, P1) coupled to said said operating means (Rll, NM6) of said third circuit (HV3) via first interconnection means (R7; Rl, D 3), the operating means (R8, NM3) of said first and second circuits being coupled to said level translator (R9/10, P2) of said third circuit via second interconnection means (T2), and that said third circuit controls said operating means of said first and second circuits via said first and second interconnection means.
Claim 25
Dependent Claim
93 words
Switching circuit according to claim 17, characterized in that said DMOS switch devices are DMOS transistors (NM4; NM7/8) of same conductivity type (N-channel) and that said operating means (R8, NM3; Rll, NM6) including a transistor (NM3; NM6) and a resistor (R8; Rll) are able to make said associated DMOS transistor(s) (NM4; NM7/8) slowly conductive by charging its/their intrinsic gate capacitance towards a positive voltage (+V3; +Vl) through said resistor and to rapidly block said DMOS transistor(s) by applying a negative voltage (-V2) to its/their gate electrode via the drain-to-source path of said transistor.
Claim 26
Dependent Claim
169 words
2 3. Switching circuit according to claims 2 1 and 22, characterized in that said negative voltage (-V2) is permanently applied to the source electrode of said transistor (NM3; NM6) of each of said operating means (R8, NM3; Rll, NM6), that said transistor (NM3) included in said first (HVl) and second (HV2) circuits is controlled by a respective one of said level translators (R5/6, Pl) and by said operating means (Rll, NM6) of said third circuit (HV3) via said first interconnection means (R7; Tl, D3), said transistor (NM6) of said third circuit being only controlled by said coupled level translator (R9/10, P2), and that said positive voltage (+V3; +Vl) is permanently applied to one end of said resistor (Rll) of said operating means (Rll, NM6) included in said third circuit, and is applied to one end of said resistor (R8) of said operating means (R8, NM3) included in said first and second circuits by said level translator (R9/10, P2) of said third circuit via said second interconnection means (T2).
Claim 27
Dependent Claim
42 words
2 4 . Matrix device according to claim 14, characterized in that said switching circuit (HVD) is realized as per any of the claims 16 to 2 3 , each of said line output terminals (OUT1/30) being said common output terminal (OUT).
References Cited (Backward Citations)
EP0078402A1
Cited
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