Semiconductor memory

Abstract

Abstract A memory structure for very large memory arrays on a chip is described where the memory array is divided into a number of subarrays. The subarrays are controlled via common word decoders and subarray decoders. The word lines of the individual subarrays are individually selectable through word line switches, and the bit lines of the subarrays are applied directly to a common line system, and interconnected in such a manner that the peripheral circuits, e.g. the data input and output circuits, can be arranged in practically any free location on the chip.

Inventors

• 👤 Siegfried Dr. Dipl.-Ing. Wiedmann

Bibliographic Details