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EP0162928A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Microprogram control method

Assignee: Fujitsu Ltd
•
Filing: 1984-11-08
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Granted: —
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Expires: 2004-11-08
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Abstract

Abstract A control memory (referred to as 'SUBOPCS', hereinaf- teri which stores information employed to generate the microprogram first address of an instruction having a suboperation code. The access to a control memory by an ordinary operation code and the access to the SUBOPCS by the suboperation code are effected simultaneously. Data respectively read out from the control memories is compiled so as to generate the first address of the microprogram. Thus, the capacity of the SUBOPCS is reduced within a range in which any reduction in the capacity does not interfere with the allocation of the microinstruction, and the microprogram first address of the instruction having the suboperation code is determined without requiring any extra time.

Inventors

  • 👤 Toshiaki Kitamura
  • 👤 Katsumi Onishi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 12:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/261; G06F9/262; G06F9/264; G06F9/265; G06F9/28; G06F9/30; G06F9/30145; G06F9/30149

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 84 words
A microprogram control system in a data processing unit which processes the instruction having the operation code and suboperation code under the microprogram control, wherein the first means retrieved by the subopc ration code and the second means for calculating the heading address of microprogram of the instruction having the suboperation code based on the branching destination data stored in said first means are provided and the heading microinstruction of instruction having the suboperation code is read by said both first and second means.
Claim 2
Dependent Claim 84 words
A microprogram control system in a data processing unit which processes the instruction having the operation code and suboperation code under the microprogram control, wherein the first means retrieved by the subopc ration code and the second means for calculating the heading address of microprogram of the instruction having the suboperation code based on the branching destination data stored in said first means are provided and the heading microinstruction of instruction having the suboperation code is read by said both first and second means.
Claim 3
Dependent Claim 64 words
A microprogram control system according to claim 1 wherein said first means is so constituted that a plurality of said branching data which are identified by said operation code are stored in the respective storing locations and said second means is so constituted that said operation code is decoded, the result is output and only one is selected among said plurality of branching data.
Claim 4
Dependent Claim 48 words
A microprogram control system according to claim 2 wherein said data processing unit which processes the instruction having the operation code and suboperation code under the microprogram control provides a third means which is retrieved by said operation code and stores the microprogram for executing said microprogram control.
Claim 5
Dependent Claim 60 words
A microprogram control system according to claim 3 wherein the heading microinstruction of instruction having suboperation code is read after determination of microaddress of relevant microinstruction, based on the result of retrieving said third means with said operation code, result of retrieving said first means with said suboperation code and result of decoding said operation code with said second means.

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