Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
112 words
I. A method of encoding and decoding a data bit characterised by the steps of: encoding said data bit by combining said data bit with an encoding bit in an encoding Exclusive-OR gate, thereby providing on encoded data bit on the output lead of said Exclusive-OR gate; transmitting said encoded data bit on a data transmission lead; decoding said encoded data bit by combining said encoded data bit with a decoding bit in a decoding Exclusive-OR gate, thereby proving a decoded data bit on the output lead of said decoding Exclusive-OR gate; whereby said encoding bit and said decoding bit may be any logical state provided they are at all times identical.
Claim 2
Dependent Claim
241 words
An encoding/decoding circuit having an input data bus comprised of N-data input lines, where N is any positive integer, characterised in that said circuit comprises: means for providing an M-bit encoding/decoding word, where M is any positive integer; a bank of N encoding Exclusive-OR gates, each of said encoding Exclusive-OR gates having a first input lead uniquely connected to one line of said input data bus, a second input lead uniquely connected to one bit of said M-bit encoding/decoding word, and having an output lead; an encoded data transmission bus comprised of N encoded data transmission lines, each said encoded data line uniquely connected to the output lead of Exclusive-OR gate of said bank of encoding Exclusive-OR gates; a bank of N decading Exclusive-OR gates, each of said decoding Exclusive-OR gates having a first Input lead uniquely connected to one of said encoded data transmission lines, a second input lead uniquely connected to one of said data bits of said M-bit encoding/decoding word, where said second input lead of each said decoding Exclusive-OR gate is connected to the same bit of said M-bit logical word as said second input lead of its associated one of said encoding Exclusive-OR gates, and each said decoding Exclusive-OR gate having an output lead; an output data bus comprised of N decoded data output lines, each said decoded output line being uniquely connected to one of said output leads of said bank of decoding Exclusive-OR gates.
Claim 3
Dependent Claim
24 words
An encoding/decoding circuit as claimed in Claim 2 further characterised in that said means for providing an M-bit encoding/decoding word is on M-bit counter.
Claim 4
Dependent Claim
25 words
An encoding/decoding circuit as claimed in Claim 2 further characterised in that said means of providing an M-bit encoding/decoding word is an M-bit pseudo-random counter.
Claim 5
Dependent Claim
75 words
An encading/decoding circuit as claimed in Claim 2 further characterised in that said means for providing an M-bit encoding/decoding word is an M-bit pseudo-random counter having a logic gate which has at least one input lead connected to one or more of the output leads of selected bits of said pseudo-random counter and has at least one output lead connected to at least one of the input leads of the bits of said pseudo-random counter.
Claim 6
Dependent Claim
248 words
An encoding/decoding circuit including an input data bus comprised of N-data input lines, where N is any positive integer, characterised in that said circuit comprises: means for providing an M-bit encoding word, where M is any positive integer; means for providing an M-bit decoding word; a bank of N encoding Exclusive-OR gates, each of said encoding Exclusive-OR gate having a first input lead uniquely connected to one line of said input data bus, a second input lead uniquely connected to one bit of said M-bit encoding word, and having an output lead; an encoded data transmission bus comprised of N encoded data transmission lines, each said encoded data line uniquely connected to the output lead one Exclusive-OR gate of said bank of encoding Exclusive-OR gates; a bank of N decoding Exclusive-OR gates, each said decoding Exclusive-OR gate having a first input lead uniquely connected to one of said encoded data transmission lines, a second input lead uniquely connected to one of said data bits of said M-bit decoding word, where said second input lead of each said decoding Exclusive-OR gate is connected to the same bit of said M-bit logical word as said second input lead of its associated one of said encoding Exclusive-OR gates, and each said decoding Exclusive-OR gate having an output lead; an output data bus comprised of N decoded data output lines, each said decoded output line being uniquely connected to one of said output leads of said bank of decoding Exclusive-OR gate banks.
Claim 7
Dependent Claim
88 words
A circuit as claimed in Claim 6 further characterised in that: said means of producing an M-bit logical word is provided by an M-bit counter for each of said decoding and encoding Exclusive-OR gate banks wherein said counter is actuated by a logical input lead which is common to both of the counters provided; and that means are provided for ensuring that the M-bit logical word contained in the said M-bit counters for said first and second Exclusive-OR gate banks are inltiallsed to the same M-bit logical word.
Claim 8
Dependent Claim
34 words
An encoding/decoding circuit as claimed in Claim 6 further characterised in that sold means for providing an M-bit encoding word and said means for providing an M-bit decoding word is an M-bit pseudo-random counter.
Claim 9
Dependent Claim
84 words
An encoding/decoding circuit as claimed in Claim 6 further characterised in that said means for providing an M-bit encoding word and said means for providing an M-bit decoding word is an M-bit pseudo-random counter having a logic gate which has at least one input lead connected to at least one of the output leads of selected bits of said pseudo-random counter and has at least one output lead connected to one or more of the input leads of the bits of said pseudo-random counter.
Claim 10
Dependent Claim
33 words
An encoding/decoding circuit as claimed in Claim 3 or Claim 7 further characterised in that said counter uses the chip enable lead of a microprocessor as the input signal which said counter counts.
Claim 11
Dependent Claim
37 words
An encoding/decoding circuit as claimed in any of Claims 4, 5, 8 or 9 further characterised in that said pseudo-random counter uses the chip enable leod of a microprocessor as the input signal which said counter counts.