EP0162234A2
Expired / Lapsed
EP
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Memory device
Assignee: NEC Corp
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Filing: 1981-07-23
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Granted: —
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Expires: 2001-07-23
Abstract
Abstract An improved memory device operable at a high speed is disclosed. The memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting the columns, a shift register arranged in parallel with the column decoder, and control means for operatively enabling the shift register, in which consecutive access to a plurality of memory cells belonging to the same selected row can be performed from the column address designated by the column decoder.
Inventors
- 👤 Satoru Kobayashi
- 👤 Shigeki Matsue
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 02:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G11C7/1006; G11C7/1015; G11C7/1018; G11C7/103; G11C7/1033; G11C7/1051; G11C7/106; G11C7/1087; G11C7/22; G11C8/00; G11C8/04; G11C8/10; G11C8/18; G11C2207/00; G11C2207/10; G11C2207/107
Claims Analysis
Total Claims: 1
Claim 1
Independent Claim
201 words
A memory device comprising a memory cell array (11, 51) including a plurality of memory cells arranged in rows and columns, a plurality of address input terminals for receiving a plurality of column address signals (Y address, AO to A7), an output line (Data input/output, Data out), a first column decoder (15, 30, 55) for determining first i output data from the data of said columns, and a shift register (15, SR, 55) coupled to said first column decoder and arranged in parallel therewith to serially read out data of the columns to said output line, the first one of the read-out data being that determined by said first column decoder, characterized in that the memory device includes a second column decoder (14, 54) and that a first portion (AO to A4) of said column address signals are supplied to said second column decoder (14, 54) to select a predetermined number (0 to L-1 in Fig. 4) of the columns, a second portion (31 in Fig. 4; A5 to A7 in Fig. 15) of said column address signals being supplied to said first column decoder (15, 30, 55) to serially read out the data from the selected number of the columns.
References Cited (Backward Citations)
US3930239A
Cited
US3969706A
Cited
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