Patent EP0161983A2 successfully refreshed from Google Patents.
EP0161983A2
Expired / Lapsed
EP
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Input protection arrangement for VLSI integrated circuit devices
Assignee: Digital Equipment Corp
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Filing: 1985-05-02
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Granted: —
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Expires: 2005-05-02
Abstract
Abstract An input protection arrangement for diverting current from high voltages due to, for example electrostatic discharges into a bonding pad of an integrated circuit chip. The chip has a bonding pad connected to a conducting path and to a source or drain region of an insulated gate field effect transistor, the other region being connected to a power bus on the chip. The conducting path runs between the source and drain regions and operates as the gate terminal of the transistor. The conducting path is insulated from the surface of the chip by a field oxide insulating layer of a substantially uniform thickness to prevent rupture of the oxide between the gate and the source and drain regions in the event of high- voltages. The source and drain regions include regions of conventional doping levels having depths corresponding to the depths of the other corresponding regions on the chip, surrounded by large wells of lower doping levels. The input pad is separated from the chip substrate by an insulating oxide layer and by a doped well of the same conductivity type as the source and drain regions of the transistor to reduce the input capacitance and prevent punch through from the pad to the substrate.
Inventors
- 👤 Chong Ming Lin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 15:31
CPC Classifications
H; H10; H10W; H10W72/00; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10W72/90
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
194 words
An input protection arrangement for an integrated circuit device on a semiconductor substrate of a first conductivity type having a bonding pad for forming an external electrical connection, said bonding pad being connected to a conducting path on said substrate for electrically connecting said pad to internal circuitry on said integrated circuit, said integrated circuit further including a reference voltage path, said input protection device comprising two regions of a second conductivity type on opposing sides of at least a portion of said conducting path, said regions and the area therebetween being covered with a layer of insulating material having a substantially uniform thickness corresponding to the thickness of field oxide, means defining apertures in said insulating layer associated with each of said regions, means for connecting one of said regions to said pad and means for connecting the other region to said reference voltage path, whereby said regions and the space therebetween define source and drain regions and the conducting path defines the gate terminal of an insulated gate field effect transistor which conducts input current associated with voltages in excess of a selected level between said pad and said reference voltage path.
Claim 2
Dependent Claim
194 words
An input protection arrangement for an integrated circuit device on a semiconductor substrate of a first conductivity type having a bonding pad for forming an external electrical connection, said bonding pad being connected to a conducting path on said substrate for electrically connecting said pad to internal circuitry on said integrated circuit, said integrated circuit further including a reference voltage path, said input protection device comprising two regions of a second conductivity type on opposing sides of at least a portion of said conducting path, said regions and the area therebetween being covered with a layer of insulating material having a substantially uniform thickness corresponding to the thickness of field oxide, means defining apertures in said insulating layer associated with each of said regions, means for connecting one of said regions to said pad and means for connecting the other region to said reference voltage path, whereby said regions and the space therebetween define source and drain regions and the conducting path defines the gate terminal of an insulated gate field effect transistor which conducts input current associated with voltages in excess of a selected level between said pad and said reference voltage path.
Claim 3
Dependent Claim
40 words
An input protection arrangement as defined in claim 1 wherein each of said regions comprises a relatively deep well of said second conductivity type, a portion of said well adjacent said connecting means being of an enhanced second conductivity type.
Claim 4
Dependent Claim
15 words
An input protection arrangement as defined in claim 1 wherein said conducting path is polysilicon.
Claim 5
Dependent Claim
15 words
An input protection arrangement as defined in claim 1 wherein said conducting path is metal.
Claim 6
Dependent Claim
40 words
An input protection arrangement as defined in claim 1 wherein said bonding pad is supported by an insulating layer, said insulating layer in turn being supported on a third region comprising a relatively deep well of said second conductivity type.
Claim 7
Dependent Claim
64 words
An input protection arrangement as defined in claim 5 wherein said bonding pad comprises a metal layer situated adjacent to the region connected thereto, said metal extending to said adjacent region and connecting thereto to provide an electrical path between said adjacent region and said conducting path to thereby interconnect said adjacent region and said gate terminal of said insulated gate field effect transistor.
Claim 8
Dependent Claim
87 words
7 . An input protection arrangement for an integrated circuit device on a semiconductor substrate of a first conductivity type having a bonding pad for forming an external electrical connection, said bonding pad being connected to a conducting path for conducting input signals to processing circuitry on said device, said pad being supported on said device by a layer of insulation, said arrangement comprising means defining a well of a second conductivity type beneath said pad and separating said pad and the insulation thereunder from said substrate.
Claim 9
Dependent Claim
87 words
7 . An input protection arrangement for an integrated circuit device on a semiconductor substrate of a first conductivity type having a bonding pad for forming an external electrical connection, said bonding pad being connected to a conducting path for conducting input signals to processing circuitry on said device, said pad being supported on said device by a layer of insulation, said arrangement comprising means defining a well of a second conductivity type beneath said pad and separating said pad and the insulation thereunder from said substrate.
Claim 10
Dependent Claim
157 words
And input protection arrangement as defined in claim 7 further comprising two regions of a second conductivity type on opposing sides of at least a portion of said conducting path, said regions and the area therebetween being covered with a layer of insulating material having a substantially uniform thickness corresponding to the thickness of field oxide, each of said regions including an inner region of enhanced doping level separated from said substrate by a well region having a reduced doping level, means defining apertures in said insulating material for connecting one of said regions to said pad and means for connecting the other region to said reference voltage path, whereby said regions and the space therebetween defined source and drain regions and the conducting path defines the gate terminal of an insulated gate field effect transistor which conducts input current associated with voltages in excess of a selected level between said pad and said reference voltage path.
Claim 11
Dependent Claim
17 words
9 . An input protection arrangement as defined in claim 8 wherein said conducting path is polysilicon.
Claim 12
Dependent Claim
17 words
10 . An input protection arrangement as defined in claim 8 wherein said conducting path is metal.
References Cited (Backward Citations)
No citation records indexed.
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