Patent EP0161446A2 successfully refreshed from Google Patents.
EP0161446A2
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EP
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Semiconductor integrated circuit comprising a protective transistor and a MOS transistor with an LDD structure
Assignee: Toshiba Corp
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Filing: 1985-03-29
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Granted: —
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Expires: 2005-03-29
Abstract
Abstract @ A protective MOS transistor (01) having a parasitic bipolar transistor for discharging to the groud (Vss) an electric charge generated in the semiconductor substrate (19) by application of a surge voltage to a high voltage power supply terminal (18) is provided between the ground (Vss) and the high voltage power supply terminal (18) of a semiconductor integrated circuit (16) including a MOS transistor with an LDD structure. The protective MOS transistor (Q1) is formed on the same semiconductor substrate (19) as the semiconductor integrated circuit (16).
Inventors
- 👤 Sumio C/O Patent Division Tanaka
- 👤 Shigeru C/O Patent Division Atsumi
- 👤 Noriyoshi C/O Patent Division Tozawa
- 👤 Toshiki C/O Patent Division Tsushima
- 👤 Taizo C/O Patent Division Okuda
- 👤 Masamichi C/O Patent Division Asano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 10:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; G; G11; G11C; G11C5/00; G11C5/14; G11C7/00; G11C7/24; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/378; H10D84/00; H10D84/101; H10D84/121; H10D89/00; H10D89/60; H10D89/601; H10D89/811
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure, comprising a semiconductor substrate (19, 28, 38) of a first conductivity type having a major surface, and a semiconductor integrated circuit (16) which is formed on a major surface region of said semiconductor substrate (19, 28, 38), includes the MOS transistor with an LDD structure and has a power supply terminal (18) and a ground point (Vss), characterized by comprising a protective MOS transistor (Ql) having a parasitic bipolar transistor (QB), which is formed on the major surface region of said semiconductor substrate (19, 28, 38), has a drain (D) connected to said power supply terminal (18), a source (S) connected to said ground point (Vss) and a gate (G), and discharges to said ground point (Vss) an electric charge generated in said semiconductor substrate (19, 28, 38) by application of a surge voltage to said power supply terminal (18).
Claim 2
Dependent Claim
153 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure, comprising a semiconductor substrate (19, 28, 38) of a first conductivity type having a major surface, and a semiconductor integrated circuit (16) which is formed on a major surface region of said semiconductor substrate (19, 28, 38), includes the MOS transistor with an LDD structure and has a power supply terminal (18) and a ground point (Vss), characterized by comprising a protective MOS transistor (Ql) having a parasitic bipolar transistor (QB), which is formed on the major surface region of said semiconductor substrate (19, 28, 38), has a drain (D) connected to said power supply terminal (18), a source (S) connected to said ground point (Vss) and a gate (G), and discharges to said ground point (Vss) an electric charge generated in said semiconductor substrate (19, 28, 38) by application of a surge voltage to said power supply terminal (18).
Claim 3
Dependent Claim
219 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure according to claim 1, characterized in that said protective MOS transistor (Ql) comprises a first impurity diffusion region (29a) of a second conductivity type which is formed in the major surface region of said semiconductor substrate (19, 28) of the first conductivity type and is connected to said ground point (Vss), a second impurity diffusion region (29b) of the second conductivity type which is formed to be separated from said first impurity diffusion region (29a) by a predetermined distance and is connected to said power supply terminal (18), a third impurity diffusion region (30) of the second conductivity type having a lower impurity concentration than that of said first and second impurity diffusion regions (29a, 29b) and contacting said second impurity diffusion region (29b), a gate insulating film (31) formed on the major surface of said semiconductor substrate (19, 28) between said first and third impurity diffusion regions (29a, 30), and a gate electrode (32) which is formed on said gate insulating film (31) and is connected to said ground point (Vss); and said parasitic bipolar transistor (QB) has said first impurity diffusion region (29a) as an emitter, said semiconductor substrate (19, 28) as a base and said second impurity diffusion region (29b) as a collector.
Claim 4
Dependent Claim
145 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure according to claim 1, characterized in that said protective MOS transistor (Ql) comprises a field oxide film (35) formed on the major surface of said semiconductor substrate (19, 28) of the first conductivity type, and first and second impurity diffusion regions (36, 37) of the second conductivity type which are formed in the major surface region of said semiconductor substrate (19, 28) and are isolated by said field oxide film (35), said first impurity diffusion region (36) being connected to said ground point (Vss), said second impurity diffusion region (37) being connected to said power supply terminal (18), and said parasitic bipolar transistor (QB) having said first impurity diffusion region (36) as an emitter, said semiconductor substrate (19, 28) as a base and said second impurity diffusion region (37) as a collector.
Claim 5
Dependent Claim
153 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure according to claim 1, characterized in that said protective MOS transistor (Ql) comprises a well region (39) of the second conductivity type formed on the major surface region of said semiconductor substrate (19, 38) of the first conductivity type, a first impurity diffusion region (40) of the first conductivity type which is formed in said well region (39) and is connected to said power supply terminal (18), and a second impurity diffusion region (41a, 41b) of the second conductivity type which has a higher impurity concentration than that of said well region (39), is formed in said well region (39) and is connected to said ground point (Vss); and said parasitic bipolar transistor (QB) has said first impurity diffusion region (40) as an emitter, said well region (39) as a base and said semiconductor substrate (19, 38) as a collector.
Claim 6
Dependent Claim
150 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure, comprising a semiconductor substrate (28, 38, 45) of a first conductivity type having a major surface, and a semiconductor integrated circuit (16) which is formed on a major surface region of said semiconductor substrate (28, 38, 45), includes the MOS transistor with an LDD structure, and has an output terminal (44) and a ground point (Vss), characterized by comprising a protective MOS transistor (Ql) having a parasitic bipolar transistor (QB), which is formed on the major surface region of said semiconductor substrate (28, 38, 45), has a drain (D) connected to said output terminal (44), a source (S) connected to said ground point (Vss) and a gate (G), and discharges to said ground point (Vss) an electric charge generated in said semiconductor substrate (28, 38, 45) by application of a surge voltage to said output terminal (44).
Claim 7
Dependent Claim
150 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure, comprising a semiconductor substrate (28, 38, 45) of a first conductivity type having a major surface, and a semiconductor integrated circuit (16) which is formed on a major surface region of said semiconductor substrate (28, 38, 45), includes the MOS transistor with an LDD structure, and has an output terminal (44) and a ground point (Vss), characterized by comprising a protective MOS transistor (Ql) having a parasitic bipolar transistor (QB), which is formed on the major surface region of said semiconductor substrate (28, 38, 45), has a drain (D) connected to said output terminal (44), a source (S) connected to said ground point (Vss) and a gate (G), and discharges to said ground point (Vss) an electric charge generated in said semiconductor substrate (28, 38, 45) by application of a surge voltage to said output terminal (44).
Claim 8
Dependent Claim
218 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure according to claim 5, characterized in that said protective MOS transistor (Ql) comprises a first impurity diffusion region (29a) of a second conductivity type which is formed in the major surface region of said semiconductor substrate (28, 45) of the first conductivity type and is connected to said ground point (Vss), a second impurity diffusion region (29b) of the second conductivity type which is formed to be separated from said first impurity diffusion region (29a) by a predetermined distance and is connected to said output terminal (44), a third impurity diffusion region (30) of the second conductivity type having a lower impurity concentration than that of said first and second impurity diffusion regions (29a, 29b) and contacting said second impurity diffusion region (29b), a gate insulating film (31) formed on the major surface of said semiconductor substrate (19, 28) between said first and third impurity diffusion regions (29a, 30), and a gate electrode (32) which is formed on said gate insulating film (31) and is connected to said ground point (Vss); and said parasitic bipolar transistor (QB) has said first impurity diffusion region (29a) as an emitter, said semiconductor substrate (19, 28) as a base and said second impurity diffusion region (29b) as a collector.
Claim 9
Dependent Claim
144 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure according to claim 5, characterized in that said protective MOS transistor (Ql) comprises a field oxide film (35) formed on the major surface of said semiconductor substrate (28, 45) of the first conductivity type, and first and second impurity diffusion regions (36, 37) of the second conductivity type which are formed in the major surface region of said semiconductor substrate (28, 45) and are isolated by said field oxide film (35), said first impurity diffusion region (36) being connected to said ground point (Vss), said second impurity diffusion region (37) being connected to said output terminal (44), and said parasitic bipolar transistor (QB) having said first impurity diffusion region (36) as an emitter, said semiconductor substrate (28, 45) as a base and said second impurity diffusion region (37) as a collector.
Claim 10
Dependent Claim
151 words
A semiconductor integrated circuit device including a MOS transistor with an LDD structure according to claim 5, characterized in that said protective MOS transistor (Ql) comprises a well region (39) of the second conductivity type formed on the major surface region of said semiconductor substrate (38, 45) of the first conductivity type, a first impurity diffusion region (40) of the first conductivity type which is formed in said well region (39) and is connected to said output terminal (44), and a second impurity diffusion region (41a, 41b) of the second conductivity type which has a higher impurity concentration than that of said well region (39), is formed in said well region (39) and is connected to said ground point (Vss); said parasitic bipolar transistor (QB) has said first impurity diffusion region (40) as an emitter, said well region (39) as a base and said semiconductor substrate (38, 45) as a collector.
References Cited (Backward Citations)
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