Packet and circuit switched communications network

Claim 2

A telecommunications switching network comprising: a plurality of units including a call controller unit; a group of data leads (607) being connected to each of the units and being commonly available for signal transmission of both call control signals between the call controller unit and the other units, and communications signals between calling and called ones of the other units; and a bus controller (Fig. 2) also being connected to each of the units for arbitrating access to the data leads by the units, so that only one unit may transmit said signals at any one instant in time.

Claim 3

A telecommunications switching network as defined in claim 1 wherein the bus controller comprises: a poll means (310, 320) for polling the units for asynchronous transmission requests; grant means (350 - 380) for granting access to the data bus for an indefinite period of time, as required for transmission of a data packet from one of the units, sometime after an occurrence of an asynchronous transmission request from said one unit; and a synchronous cycle means (410 - 420) being responsive to an occurrence of a synchronous request signal from any of the units, for generating a synchronous cycle signal for a predetermined time commencing at a preset time after said occurrence, for inhibiting any data packet transmission from any one of the units and for enabling a synchronous data transmission via the data leads during said predetermined period of time.

Claim 4

A telecommunications switching network as defined in claim 1 wherein the bus controller is connected to the units via a group of address leads (610) and a plurality of control leads (614 - 618, 221 - 225) and wherein the bus controller comprises: a poll means including an address counter (311) for periodically generating a series of addresses for polling the units one after the other via the address leads; and a grant means including, a queue storage means (371) being responsive to an occurance of an asynchronous transmission request in the form of a request flag having been asserted on a request of one of the control leads (221) by a polled unit for storing the address corresponding to the polled unit; and an address select means (320) being responsive to at least one address having been stored in the queue storage means for inhibiting the address counter and for causing the address to be withdrawn from the queue storage means and asserted on the address leads coincident with generating a grant flag on a grant one of the control leads (214, 614).

Claim 5

A telecommunication switching network as defined in claim 3 wherein the bus controller further comprises: a synchronous cycle means (400) being responsive to an occurrence of a synchronous request signal from any of the units, for generating a synchronous cycle signal for a predetermined time commencing at a pre-set time after said occurrence, for inhibiting any data packet transmission from any one of the units for and enabling a synchronous data transmission via the data leads during said predetermined period of time.

Claim 6

A telecommunications switching network as defined in claim 4 wherein the bus controller further comprises: means (205) for generating clock and frame signals on clock and frame ones of the control leads, each frame signal having a period corresponding to a sum of a predetermined plurality of n clock signal periods; and wherein the synchronous cycle means comprises: a first gating circuit (412, 416) being setable to define a portion of each frame period within which synchronous cycle signals are permitted and in response to the clock and frame signals for generating an enable signal during each portion; and a second gating circuit (410, 411, 412) being responsive to the clock signals and the enable signal for generating the synchronous cycle signal, on a synchronous cycle one of the control leads, being delayed a predetermined period of time from each occurrence of the synchronous request signal on a synchronous request one of the control leads.

Claim 7

A telecommunications switching network as defined in claim 3 wherein the poll means further comprises: a poll range limiting means (312, 313) , being setable with first and second limit corresponding to limits of a range of addresses, for causing the counter to be loaded with one of the limits in response to the counter having attained a count corresponding to the other of the limits, whereby in operation polling and subsequent grants may be limited to a population of less than a maximum possible number of units in the switching network.

Claim 8

A telecommunications switching network as defined in claim 3 wherein the grant means further comprises: a disable unit address circuit (354) being setable with addresses for defining ones of the units being restricted from operation, and being responsive to an occurrence of a corresponding unit address on the address leads to prevent storage of the corresponding unit address in the queue storage means.

Claim 9

A telecommunications switching network as defined in claim 3 wherein the grant means further comprises: a wrap around circuit (357) being responsive to the request flag for preventing storage in the queue storage means of an address corresponding to an address presently stored in the queue storage means.

Claim 10

A telecommunications switching network as defined in claim 3 wherein the grant means further comprises: a wrap around circuit (357) including a memory location corresponding to each of the addresses providable from the poll means, each memory location being operable to be set in the combined presence of its address and an assertion of the request flag and to be reset in the presence of its address while the request flag is unasserted, and gating means (360) for generating an inhibit signal, in response to each address occurrence for which the corresponding memory location was set, for preventing storage of the corresponding address in the queue storage means.

Claim 11

A telecommunications switching network as defined in claim 3 wherein each of the plurality of units is connected by a respective bus/unit interface circuit (Fig. 7) to transmit and receive call control signals and communication signals via the data leads, to be responsive to signals on various of the control leads and to originate signals on various of the control leads, the bus/unit interface circuit comprising: matching means (750) for generating an address match signal for use in the unit in response to a correspondence between an address on the address leads and a preset address of the bus/unit interface circuit; a request gating means (721, 751) for asserting the request flag on the request one of the control leads in response to a request signal from the unit and a pulse of the clock signal immediately following the address match signal from the matching means; a grant latch (752, 753, 757) for generating a unit grant signal commencing with a pulse of the clock signal immediately following a coincidence of the grant flag on the grant one of the control leads and the address match signal from the matching means, and thereafter for terminating generation of the unit grant signal commencing with a pulse of the clock signal immediately following a subsequent occurrence of the grant flag; a done gating means (725) for asserting a done flag signal on a done flag one of the control leads in response to a done unit signal from the unit occurring in the presence of the unit grant signal from the grant latch; transmission gating means (722, 723, 726, 727, 758) for transmitting call control signals and/or communication signals from the unit to the data leads in response to either of the unit grant signal from the grant latch or a cycle match signal from the unit, and for alternately transmitting signals from the data leads to the unit in the absence of both the unit grant signal and the cycle match signal.

Claim 12

A telecommunications switching network as defined in claim 1 wherein the bus controller is connected to the units via a group of address leads (210) and a plurality of control leads (213 - 218, 221, 225), the bus controller comprising: a timing circuit (205) for generating frame and clock signals, the clock signal having a period defining a period of a bus cycle, there being n clock signal periods in the period of the frame signal; a selection circuit (320, 380) for selecting one of a poll circuit (310 - 316) and a grant circuit (370, 371, 378) as a source of addresses for transmission via the address leads in response to the clock signal, a state of a status signal from the grant circuit, and a done flag on a done one of the control leads; a synchronous cycle circuit (Fig. 4) for defining bus cycle occurrences of zero through n during each frame period in response to the clock signal and the frame signal, the synchronous cycle circuit being responsive to a synchronous request signal on a synchronous request one of the control leads (224) for asserting a synchronous cycle signal on a synchronous cycle one of the control leads (215) during a bus cycle in a setable range of the defined bus cycle occurrence; the poll circuit comprising: an address generating means (310, 313) for asserting addresses, within a setable range of addresses, one after another on the address bus and at the rate of the clock signal while selected by the selection circuit; a grant circuit comprising: temporary storage means (350) for synchronizing an occurrence of a request flag signal on a request flag one of the control leads (221) with an associated address having already been received from the address bus, a queue storage means (370, 378) for storing addresses from the temporary storage means one after another each storing being in response to the presence of an associated request flag signal and for asserting the stored addresses on the address bus one after another each assertion being in response to a grant flag from the select circuit on the grant one of the control leads (214), the queue storage means including at least one status output lead (375) being connected to the select circuit for indicating the queue storage means as being in one of a full state or an empty state.

Claim 13

A telecommunications switching network as defined in claim 11 wherein each of the plurality of units is connected by a respective bus/unit interface circuit to transmit and receive call control signals and communication signals via the data leads, to be responsive to signals on various of the control leads and to originate signals on various of the control leads, the bus/unit interface circuit comprising: matching means (750) for generating an address match signal for use in the unit in response to a correspondence between an address on the address leads and a preset address of the bus/unit interface circuit; a request gating means (721, 751) for asserting the request flag on the request one of the control leads in response to a request signal from the unit and a pulse of the clock signal immediately following the address match signal from the matching means; a grant latch (752, 753, 757) for generating a unit grant signal commencing with a pulse of the clock signal immediately following a coincidence of the grant flag on the grant one of the control leads and the address match signal from the matching means, and thereafter for terminating generation of the unit grant signal commencing with a pulse of the clock signal immediately following a subsequent occurrence of the grant flag; a done gating means (725) for asserting the done flag signal on a done flag one of the control leads in response to a done unit signal from the unit occurring in the presence of the unit grant signal from the grant latch; transmission gating means (722, 723, 726, 727, 758) for transmitting call control signals and/or communication signals from the unit to the data leads in response to either of the unit grant signal from the grant latch or a cycle match signal from the unit, and for alternately transmitting signals from the data leads to the unit in the absence of both the unit grant signal and the cycle match signal.

Claim 14

A telecommunications network as defined in claim 1 wherein the data leads and the bus controller comprise a pair combination (A) which is duplicated (B) and wherein each of the units is connected via a pair of a bus/unit interface circuits (Fig. 7) to the data leads of each pair combination, each of the bus controllers including a use circuit (204) for arbitrating which of the bus controllers is active and inactive respectively, each use circuit being for generating a use signal in the absence of a use signal from the other bus controller for use by each of the bus/unit interface circuits for enabling communications between each unit and the data leads in current use.