Patent EP0160428A2 successfully refreshed from Google Patents.
EP0160428A2
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Self-testing data processing system with system test master arbitration
Assignee: Texas Instruments Inc
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Filing: 1985-04-09
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Granted: —
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Expires: 2005-04-09
Abstract
Abstract The present invention relates to a self testing data processing system which includes a communications bus (112) for enabling communication between intelligent and nonintelligent data processing circuits. The communications bus (112) has connection slots for connection of these data processing circuits, each such connection having a unique electrically readable slot number (114). Each data processing circuit has a identity memory (240) which indicates whether or not that circuit can become a system test master. Each intelligent data processing circuit (200) has additional data in its identity memory (240) indicating whether or not it has passed a circuit self test. Each intelligent data processing circuit (200) has a data processing unit (220) which performs its circuit self test program (252) upon initial application of electric power and notes the result in its identity memory (240). The system test master is then determined by arbitration. The intelligent data processing circuit (200) which has passed its circuit self test and occupies the lowest slot number becomes the system test master. The system test master performs a system self test program (253). Each nonintelligent data processing circuit includes a circuit test program written in an intermediate level interpretable test language. Each intelligent data processing circuit (200) includes an interpreter program (254) for interpretation of the test language. The system test master tests each nonintelligent data processing circuit by recall, interpretation and execution of the test program of that nonintelligent data processing circuit.
Inventors
- 👤 Gerald E. Laws
- 👤 Keith E. Diefendorff
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 21:34
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2284; G06F11/006; G06F11/2205; G06F11/2221; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0669; G06F12/0676
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
221 words
A self testing data processing system comprising: a communications bus having a plurality of connection slots, each connection slot having a unique electrically readable slot number, said communications bus for bidirectional communications between said slots; a plurality of intelligent data processing circuits, each intelligent data processing circuit connected to one of said slots and having an identity memory means and a testing means, said identity memory means having identity data indicating said intelligent data processing circuit can be a system test master and self test data indicating whether or not said intelligent data processing circuit has passed a circuit self test, said testing means having a circuit testing means for self testing said intelligent data processing circuit and loading data into said identity memory means indicative of whether or not said intelligent data processing circuit has passed said circuit self test, a master arbitration means for reading said identity memory means of other slots and deferring system test control if said intelligent data processing circuit has failed its circuit self test or if said identity memory means of any lower slot number has identity data indicating it can be a system test master and self test data indicating it has passed its circuit self test, and system test master means for controlling system test if system test control is not deferred.
Claim 2
Dependent Claim
221 words
A self testing data processing system comprising: a communications bus having a plurality of connection slots, each connection slot having a unique electrically readable slot number, said communications bus for bidirectional communications between said slots; a plurality of intelligent data processing circuits, each intelligent data processing circuit connected to one of said slots and having an identity memory means and a testing means, said identity memory means having identity data indicating said intelligent data processing circuit can be a system test master and self test data indicating whether or not said intelligent data processing circuit has passed a circuit self test, said testing means having a circuit testing means for self testing said intelligent data processing circuit and loading data into said identity memory means indicative of whether or not said intelligent data processing circuit has passed said circuit self test, a master arbitration means for reading said identity memory means of other slots and deferring system test control if said intelligent data processing circuit has failed its circuit self test or if said identity memory means of any lower slot number has identity data indicating it can be a system test master and self test data indicating it has passed its circuit self test, and system test master means for controlling system test if system test control is not deferred.
Claim 3
Dependent Claim
101 words
A self testing data processing system as claimed in Claim 1, wherein: each intelligent data processing circuit includes means for electrically reading said unique slot number and means for generating data on said communications bus from said memory means in responce to a read memory signal on said communications bus specifying an address which bears a predetermined relationship to said slot number, and wherein said master arbitration means includes means for reading said identity memory means of another slot by generating on said communications bus a read memory signal specifying an address which bears said predetermined relationship to said slot number.
Claim 4
Dependent Claim
86 words
A self testing data processing system as claimed in Claim 1. wherein: said identity memory means of each Intelligent data processing circuit has further self test data indicating whether or not circuit self test is in progress; and said master arbitration means of each intelligent data processing circuit determines that an intelligent data processing circuit in another slot has failed its circuit self test if the self test data for that slot indicates circuit self test in progress for longer than a predetermined period of time.
Claim 5
Dependent Claim
29 words
A self testing data processing system as claimed in Claim 1, wherein: said testing means of each Intelligent data processing circuit is actuated upon initial application of electric power.
Claim 6
Dependent Claim
32 words
A self testing data processing system as claimed in Claim 1, wherein: said testing means of each intelligent data processing circuit is actuated via a system reset command on said communications bus.
Claim 7
Dependent Claim
93 words
A self testing data processing system as claimed in Claim 1. further comprising: at least one nonintelligent data processing circuit, each nonintelligent data processing circuit connected to one of said slots and having an identity memory means readable from said communications bus. said identity memory means having identity data indicating said nonintelli g ent data processing circuit cannot be a system test master; and wherein said system test master means of each intelligent data processing circuit further includes means for testing said nonintelliaent data processing circuits if system test control is not deferred.
Claim 8
Dependent Claim
64 words
A self testing data processing system as claimed in Claim 6. wherein: each nonintelligent data processing circuit includes means for electrically reading said uniaue slot number and means for generating data on said communications bus from said identity memory means in response to a read memory signal on said communications bus specifying an address which bears a predetermined relationship to said unique slot number.
Claim 9
Dependent Claim
264 words
An intelligent data processing circuit comprising: a bus connector means for connection to a communication bus for bidirectional communication, said bus connector means having slot number reading means for reading an electrically readable slot number from said communications bus; an identity memory means connected to said bus connector means for generating data on said communications bus in response to a read signal specifying an address which bears a predetermined relationship to said slot number, said data including identity data indicating that said intelligent data processing circuit can be a system test master and self test data indicating whether or not said intelligent data processing circuit has passed a circuit self test; and a testing means connected to said bus connector means for bidirectional communication with said communication bus including circuit testing means for self testing said intelligent data processing circuit and loading data into said identity memory means indicating whether or not said intelligent data processing circuit passed said circuit self test, master arbitration means for generating on said communications bus read signals specifying addresses which bear said predetermined relationship to other slot numbers treating any response from said communications bus as identity data and self test. data and deferring system test control if said intelligent data processing circuit has failed its circuit self test or if any lower slot number had identity data indicating it can be a system master and self test data indicating it has passed Its circuit self test, and a system test master means for controlling system test via said communications bus if system test control is not deferred.
Claim 10
Dependent Claim
264 words
An intelligent data processing circuit comprising: a bus connector means for connection to a communication bus for bidirectional communication, said bus connector means having slot number reading means for reading an electrically readable slot number from said communications bus; an identity memory means connected to said bus connector means for generating data on said communications bus in response to a read signal specifying an address which bears a predetermined relationship to said slot number, said data including identity data indicating that said intelligent data processing circuit can be a system test master and self test data indicating whether or not said intelligent data processing circuit has passed a circuit self test; and a testing means connected to said bus connector means for bidirectional communication with said communication bus including circuit testing means for self testing said intelligent data processing circuit and loading data into said identity memory means indicating whether or not said intelligent data processing circuit passed said circuit self test, master arbitration means for generating on said communications bus read signals specifying addresses which bear said predetermined relationship to other slot numbers treating any response from said communications bus as identity data and self test. data and deferring system test control if said intelligent data processing circuit has failed its circuit self test or if any lower slot number had identity data indicating it can be a system master and self test data indicating it has passed Its circuit self test, and a system test master means for controlling system test via said communications bus if system test control is not deferred.
Claim 11
Dependent Claim
74 words
An intelligent data processing circuit as claimed in Claim 8. wherein: said identity memory means has further self test data indicating whether or not a circuit self test is in progress; and said master arbitration means determines that an intelligent data processing circuit in another slot has failed its circuit self test if the self test data for that slot indicates circuit self test in progress for longer than a predetermined period of time.
Claim 12
Dependent Claim
22 words
An intelligent data processing circuit as claimed in Claim 8. wherein: said testing means is actuated upon initial application of electrical power.
Claim 13
Dependent Claim
25 words
An intelligent data processing circuit as claimed in Claim 12. wherein: said testing means is actuated via a system reset command on said communications bus.
Claim 14
Dependent Claim
145 words
A self testing data processing system comprising: a communications bus having a plurality of connection slots for bidirectional communication between said slots; at least one nonintelligent data processing circuit. each nonintelligent data processing circuit connected to one of said slots and having a test memory means connected to and readable from said communications bus, said test memory means having a diagnostic program, written in an intermediate level interpretable test language, stored therein for testing said nonintelligent data processing circuit; and at least one intelligent data processing circuit connected to said communications bus and having an interpreter program and a testino means. said interpreter program for interpreting said intermediate level interpretable test language, and said testing means for testing said at least one nonintelligent data processing circuit via said communications bus by recall, interpretation and execution of said test program stored in said diagnostic memory means.
Claim 15
Dependent Claim
145 words
A self testing data processing system comprising: a communications bus having a plurality of connection slots for bidirectional communication between said slots; at least one nonintelligent data processing circuit. each nonintelligent data processing circuit connected to one of said slots and having a test memory means connected to and readable from said communications bus, said test memory means having a diagnostic program, written in an intermediate level interpretable test language, stored therein for testing said nonintelligent data processing circuit; and at least one intelligent data processing circuit connected to said communications bus and having an interpreter program and a testino means. said interpreter program for interpreting said intermediate level interpretable test language, and said testing means for testing said at least one nonintelligent data processing circuit via said communications bus by recall, interpretation and execution of said test program stored in said diagnostic memory means.
Claim 16
Dependent Claim
35 words
A self testing data processing system as claimed in Claim 12. wherein: each intelligent data processing circuit includes a processor means for performing general purpose data processing tasks under program control in a native language.
Claim 17
Dependent Claim
75 words
A self testing data processing system as claimed in Claim 13, wherein: said at least one intelligent data processing circuit includes a plurality of intelligent data processing circuits of at least two differing types, each of said differing types having ciffering native languages and differing test interpreter programs, whereby the testing of said at least one nonintelligent data processing circuit is independent of the native language of any one of said intelligent data processing circuits.
Claim 18
Dependent Claim
54 words
A self testing data processing system as claimed in Claim 12. wherein: said at least one nonintelligent data processing circuit includes a plurality of nonintelligent data processing circuits of at least two differing types, each of said differing types of nonintelligent data processing circuits having differing diagnostic programs stored in their test memory means.
Claim 19
Dependent Claim
80 words
A self testing data processing system as claimed in Claim 12. further comprising: at least one mass memory means connected to said communication bus having a system test program, written in said intermediate level interpretable test language, stored therein for testing said data processing system, whereby said at least one intelligent data processing circuit can test said data processing system via said communications bus by recall, interpretation and execution of said system test program stored in said mass memory means.
Claim 20
Dependent Claim
38 words
A nonintelligent data processing circuit having an application component and a test memory for storing a diagnostic program therein, said diagnostic program for testing said application component being written in a processor independent intermediate level interpretable test language.
Claim 21
Dependent Claim
38 words
A nonintelligent data processing circuit having an application component and a test memory for storing a diagnostic program therein, said diagnostic program for testing said application component being written in a processor independent intermediate level interpretable test language.
Claim 22
Dependent Claim
83 words
An intelligent data processing circuit for connection to and bidirectional communication with a communications bus having a processor means for performing general purpose data processing tasks under program control in a native language, an interpreter means for interpreting an intermediate level interpretable test language independent of said native language, and a testing means for testing another circuit connected to said communications bus by recall via said communications bus, interpretation and execution of a test program written in said intermediate level interpretable diagnostic language.
Claim 23
Dependent Claim
83 words
An intelligent data processing circuit for connection to and bidirectional communication with a communications bus having a processor means for performing general purpose data processing tasks under program control in a native language, an interpreter means for interpreting an intermediate level interpretable test language independent of said native language, and a testing means for testing another circuit connected to said communications bus by recall via said communications bus, interpretation and execution of a test program written in said intermediate level interpretable diagnostic language.
References Cited (Backward Citations)
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