Patent EP0159654A2 successfully refreshed from Google Patents.
EP0159654A2
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EP
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Amplifier circuit
Assignee: Toshiba Corp
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Filing: 1985-04-16
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Granted: —
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Expires: 2005-04-16
Abstract
Abstract In a disclosed amplifier circuit, P channel MOS transistors (M11, M12), as input elements, are connected at the sources to the emitters of bipolar transistors (Q11, Q12).
Inventors
- 👤 Yasuhiro C/O Patent Division Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 16:01
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F1/00; H03F1/08; H03F1/22; H03F1/223
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
117 words
An amplifier circuit comprising: a high potential power source terminal (Vcc); a low potential power source terminal (VEE); a pair of P channel MOS transistors (M11, M12) of which the sources are connected to said low potential power source terminal, and the gates are connected for reception of a differential input signal; a pair of bipolar transistors (Qll, Q12) which are connected at the emitters to the sources of said P channel MOS transistors; a base bias power source (21) connected to the bases of said bipolar transistors; loads (22, 23) connected respectively to the collectors of said bipolar transistors; and said bipolar transistors being respectively connected through said loads to said high potential power source terminal.
Claim 2
Dependent Claim
117 words
An amplifier circuit comprising: a high potential power source terminal (Vcc); a low potential power source terminal (VEE); a pair of P channel MOS transistors (M11, M12) of which the sources are connected to said low potential power source terminal, and the gates are connected for reception of a differential input signal; a pair of bipolar transistors (Qll, Q12) which are connected at the emitters to the sources of said P channel MOS transistors; a base bias power source (21) connected to the bases of said bipolar transistors; loads (22, 23) connected respectively to the collectors of said bipolar transistors; and said bipolar transistors being respectively connected through said loads to said high potential power source terminal.
Claim 3
Dependent Claim
100 words
An amplifier circuit according to claim 1, characterized in that said base bias power source (1) comprises a current source (25) whose input terminal is connected to said high potential power source terminal, and a current mirror circuit (M13, M14), one input terminal of the current mirror circuit being connected to an output terminal of the current source and the bases of said bipolar transistors, the other input terminal of the current mirror circuit being connected to the drains of said MOS transistors, and output terminals of the current mirror circuit being connected to said low potential power source terminal.
Claim 4
Dependent Claim
104 words
An amplifier circuit according to claim 2, characterized in that said current mirror circuit comprises first and second N channel MOS transistors (M13, M14), the drain of the first N channel MOS transistor being connected to the gate thereof and the drains of said first and second P channel MOS transistors, the drain of the second N channel MOS transistor being connected to the output terminal of said current source, the sources of the first and second N channel MOS transistors being connected to said low potential power source terminal, and the gates of the first and second N channel MOS transistors being interconnected.
References Cited (Backward Citations)
No citation records indexed.
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