Patent EP0157489A2 successfully refreshed from Google Patents.
EP0157489A2
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EP
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Amorphous silicon field-effect transistors, method for their manufacture and their use in liquid crystal display devices
Assignee: ZF International UK Ltd
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Filing: 1985-02-25
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Granted: —
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Expires: 2005-02-25
Abstract
Abstract @ An a-Si FET comprising electrically conductive source and drain regions 25, 26 supported by an insulating substrate 21; a layer of amorphous silicon 28 which is separately deposited in a space between said source and drain regions 25, 26 so as to engage the source and drain regions; source and drain electrodes 23, 24 electrically connected with said source and drain regions respectively; a gate electrode 20 disposed adjacent said layer of amorphous silicon; and an insulating layer 22 separating the gate electrode from the amorphous silicon layer; the arrangememt being such that, in the ON state of the FET, a direct current-path 27-27' is established in the layer of amorphous silicon which is disposed in said space. A low cost, low- temperature substrate such as soda glass may be used and the a-Si FET may be of the thin film type. Such an a-Si FET can be used in an LCD device which is addressed using one or more of the FET's.
Inventors
- 👤 Simon Nicholas Crowther
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 15:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/6704; H10D30/6713; H10D86/00; H10D86/40; H10D86/60; G02F2202/00; G02F2202/10; G02F2202/103
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
125 words
An a-Si FET comprising electrically conductive source and drain regions (25, 25') supported by an insulating substrate (21); a layer (28) of amorphous silicon which is separately deposited in a space between said source and drain regions (25, 25') so as to engage the source and drain regions (25, 25'); source and drain electrodes (23, 24) electrically connected with said source and drain regions (25, 25') respectively; a gate electrode (20) disposed adjacent said layer (28) of amorphous silicon; and an insulating layer (22) separating the gate electrode (20) from the amorphous silicon layer (28); the arrangement being such that, in the ON state of the FET, a direct current-path is established in the layer (28) of amorphous silicon which is disposed in said space.
Claim 2
Dependent Claim
125 words
An a-Si FET comprising electrically conductive source and drain regions (25, 25') supported by an insulating substrate (21); a layer (28) of amorphous silicon which is separately deposited in a space between said source and drain regions (25, 25') so as to engage the source and drain regions (25, 25'); source and drain electrodes (23, 24) electrically connected with said source and drain regions (25, 25') respectively; a gate electrode (20) disposed adjacent said layer (28) of amorphous silicon; and an insulating layer (22) separating the gate electrode (20) from the amorphous silicon layer (28); the arrangement being such that, in the ON state of the FET, a direct current-path is established in the layer (28) of amorphous silicon which is disposed in said space.
Claim 3
Dependent Claim
41 words
An a-Si FET as claimed in claim 1 wherein said source, drain and gate electrodes (23, 24, 20) are mounted directly on the insulating substrate (21) with said source and drain regions (25, 25') disposed on said electrodes (23, 24) respectively.
Claim 4
Dependent Claim
22 words
An a-Si FET as claimed in claim 1 or 2, wherein said insulating layer (22) is disposed on said gate electrode (20).
Claim 5
Dependent Claim
30 words
An a-Si FET as claimed in claim 1, 2 or 3 wherein said layer (28) of amorphous silicon completely fills the space between said source and drain regions (25, 25').
Claim 6
Dependent Claim
30 words
An a-Si FET as claimed in claim 1, wherein said source and drain regions are mounted directly on the insulating substrate and the respective electrodes are mounted on said regions.
Claim 7
Dependent Claim
51 words
An a-Si FET as claimed in any preceding claim, wherein the substrate (21) is soda-glass; the source, gate and drain electrodes (23, 24, 20) are made of a metallic conductor, the insulating layer (22) is made of silicon nitride; and the source and drain (25, 25') are highly doped amorphous silicon.
Claim 8
Dependent Claim
50 words
An a-Si FET as claimed in any preceding claim, wherein the source and drain regions (25, 25') and the space therebetween are formed by depositing an electrically conductive layer and then removing part of said electricallly conductive layer so as to define the space and said source and drain regions.
Claim 9
Dependent Claim
134 words
A liquid crystal display device addressed using one or more a-Si FETS each comprising electrically conductive source and drain regions (25, 25') supported by an insulating substrate (30); a layer (28) of amorphous silicon which is separately deposited in a space between said source and drain regions (25, 25') so as to engage the source and drain regions (25,25'); source and drain electrodes (23, 24) electrically connected with said source and drain regions (25, 25') respectively; a gate electrode (20) disposed adjacent said layer (28) of amorphous silicon; and an insulating layer (22) separating the gate electrode (20) from the amorphous silicon layer (28); the arrangement being such that, in the ON state of the FET, a direct current-path is established in the layer (28) of amorphous silicon which is disposed in said space.
Claim 10
Dependent Claim
134 words
A liquid crystal display device addressed using one or more a-Si FETS each comprising electrically conductive source and drain regions (25, 25') supported by an insulating substrate (30); a layer (28) of amorphous silicon which is separately deposited in a space between said source and drain regions (25, 25') so as to engage the source and drain regions (25,25'); source and drain electrodes (23, 24) electrically connected with said source and drain regions (25, 25') respectively; a gate electrode (20) disposed adjacent said layer (28) of amorphous silicon; and an insulating layer (22) separating the gate electrode (20) from the amorphous silicon layer (28); the arrangement being such that, in the ON state of the FET, a direct current-path is established in the layer (28) of amorphous silicon which is disposed in said space.
Claim 11
Independent Claim
78 words
A method of manufacturing an a-Si FET as claimed in claimi , including the steps of depositing a doped layer which is destined to form the source and drain regions (25, 25') supported by said insulating substrate (21), removing part of said doped layer to define said source and drain regions (25, 25') with a space therebetween, and depositing an intrinsic a-Si layer (28) in said space so as to engage the source and drain regions (25, 25').
Claim 12
Dependent Claim
123 words
A method as claimed in claim 9, comprising the following steps in sequence:- 1. depositing metal electrode material layer on a substrate 21, 2. masking an electrode pattern photolithographically, 3. etching the electrode pattern and de-masking, 4. depositing a gate insulating material layer, 5. masking an insulating pattern photolithographically, 6. etching a gate insulating pattern and de-masking, 7. depositing a doped layer which is destined to form the source and drain regions (25, 25'), 8. masking a source and drain region pattern photolithographically, 9. etching the source and drain region pattern and de-masking, 10. depositing an intrinsic a-Si layer (28) in the space between the source and drain regions, 11. masking an a-Si layer pattern photolithographically, 12. etching a-Si layer pattern and de-masking.
References Cited (Backward Citations)
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