Charge transfer device and method

Claim 1

A device for effecting the transfer of charge carriers in a solid substrate (54) between a first location (beneath 56) and a second location (beneath 46), wherein the charge carriers (64) are accumulated in said first location, characterized b y a) means (52) for providing a first channel potential level (68) in said substrate beneath a third location (beneath 52) lieing on a path (e.g. line 3-3) between said first and second locations; b) means (52) for providing a second channel potential level (72) beneath said third location, whereat said second channel potential level (72) is lower than said first channel potential level (68); and c) means (50) for providing a constant third channel potential level (66) beneath a fourth location (beneath 50) lieing in said path between said first and third locations whereat said third channel potential level (66) is lower than said first channel level (68) but not lower than said second channel potential level (72).

Claim 2

A device for effecting the transfer of charge carriers in a solid substrate (54) between a first location (beneath 56) and a second location (beneath 46), wherein the charge carriers (64) are accumulated in said first location, characterized b y a) means (52) for providing a first channel potential level (68) in said substrate beneath a third location (beneath 52) lieing on a path (e.g. line 3-3) between said first and second locations; b) means (52) for providing a second channel potential level (72) beneath said third location, whereat said second channel potential level (72) is lower than said first channel potential level (68); and c) means (50) for providing a constant third channel potential level (66) beneath a fourth location (beneath 50) lieing in said path between said first and third locations whereat said third channel potential level (66) is lower than said first channel level (68) but not lower than said second channel potential level (72).

Claim 5

A device according to one of the preceding claims wherein the first location is provided beneath a detector (56) characterized by d) a CTD shift register (46,48) on said substrate (54) wherein periodical clocking signals are applied to portions of said CTD shift register; e) a first gate (50) overlying a first portion of said substrate (54) between said detector (56) and said CTD shift register (46,48), and being adapted to have a substantially constant voltage applied thereto; and f) a second gate (52) overlying a second portion of said substrate between said first gate (50) and said CTD shift register (46,48), and being adapted to have a voltage pulse applied thereto at intervals which are at least twice the duration of the period of the clocking signals.

Claim 9

A device according to one of the preceding claims, wherein the first location in said substrate (54) lies beneath a detector (56) and the second location in said substrate lies beneath one of a plurality of clocked gates (46), characterized in that g ) said detector (56) and said clocked gates (46) overlie separate areas of said substrate (54) and each of said clocked gates is impressed with more than two voltage clocking signals during a predetermined time interval; h) a transfer gate (52) overlying a first portion of said substrate, being positioned proximate one of said clocked gates (46), having a transfer voltage impressed thereupon at most once during said predetermined time interval and being adapted to transfer at least some of any of said charge carriers (64) in said substrate from the location beneath said transfer gate (52) to a location beneath said one of said clocked gates (46) when said transfer voltage is impressed upon said transfer gate; and i) a reset gate (50) overlying a second portion of said substrate, being positioned proximate said transfer gate (52) and proximate said detector (56), having a substantially constant voltage impressed thereupon during said predetermined time interval and being adapted to transfer at least some of any of said charge carriers (64) in said location beneath said detector (56) to said location beneath said transfer gate (52) when said transfer voltage is impressed upon said transfer gate.

Claim 10

A method for effecting the transfer of charge carriers (64) in a solid substrate (54) having a principal surface (55), said charge carriers (64) being transferred between beneath a first location (beneath 56) on said surface (55) and beneath a second location (beneath 46) on said surface, wherein said charge carriers (64) are accumulated in said substrate beneath said first location (beneath 56) and the channel potential (70) in said substrate beneath said second location is determined by a plurality of clocking signals, characterized by j) providing a first channel potential level (68) in said substrate beneath a third location (beneath 52) on said surface, said third location lieing on a path (e.g. line 3-3) along said surface between said first (beneath 56) and second locations (beneath 46); k) providing a second channel potential level (72) beneath said third location (beneath 52) in place of said first channel potential level (68) at selected times, wherein the intervals between said selected times each include at least three of said clocking signals, at least one of said clocking signals occurs while said second channel potential level (72) is provided and said second channel potential level (72) is lower than said first channel potential level (68); and 1) providing a constant third channel potential level (66) beneath a fourth location (beneath 50) on said surface (55), said fourth location lieing on said path (e.g. line 3-3) between said first (beneath 56) and third (beneath 46) locations and said third channel potential level (66) being lower than said first channel potential level (68) but not lower than said second channel potential level (72).

Claim 11

A method for effecting the transfer of charge carriers (64) in a solid substrate (54) having a principal surface (55), said charge carriers (64) being transferred between beneath a first location (beneath 56) on said surface (55) and beneath a second location (beneath 46) on said surface, wherein said charge carriers (64) are accumulated in said substrate beneath said first location (beneath 56) and the channel potential (70) in said substrate beneath said second location is determined by a plurality of clocking signals, characterized by j) providing a first channel potential level (68) in said substrate beneath a third location (beneath 52) on said surface, said third location lieing on a path (e.g. line 3-3) along said surface between said first (beneath 56) and second locations (beneath 46); k) providing a second channel potential level (72) beneath said third location (beneath 52) in place of said first channel potential level (68) at selected times, wherein the intervals between said selected times each include at least three of said clocking signals, at least one of said clocking signals occurs while said second channel potential level (72) is provided and said second channel potential level (72) is lower than said first channel potential level (68); and 1) providing a constant third channel potential level (66) beneath a fourth location (beneath 50) on said surface (55), said fourth location lieing on said path (e.g. line 3-3) between said first (beneath 56) and third (beneath 46) locations and said third channel potential level (66) being lower than said first channel potential level (68) but not lower than said second channel potential level (72).