Patent EP0156316A2 successfully refreshed from Google Patents.
EP0156316A2
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EP
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Memory device with data access control
Assignee: Toshiba Corp
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Filing: 1985-03-22
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Granted: —
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Expires: 2005-03-22
Abstract
Abstract A memory device in accordance with the present invention comprises a memory (32) which is constructed by a plurality of small memories,to which address signals are supplied commonly. And in addition, each memory is equipped independently with a data input and output line and a write and read control signal line, and the data with a plurality of bits that make up a word are memorized dispersedly at each of these small memories. The memory device further includes a multiplexer (36) for receiving the address signals and the bit width indication signal to output selectively address signals corresponding to the desired bit numberfrom the two kinds of bit numbers, a register (40) for outputting, when making access to the bits with the first bit number of the two kinds of bit number, a write and read control signal to indicate the bits of the first bit number, to the write and read control signal line in the memory, a decoder (38) for receiving, when making access to the bits with the second bit number alone, the address signals that are not outputted from the selection means (36) as a position selection signal, and outputs, according to its address content, a write and read Control signal to indicate the bits with the second bit number to the write and read control signal line in the memory, and a CPU (34) for supplying through an 10 register (46) the bit width indication signal, in accordance with an R/W signal, to the input and output circuit (42) which controls the input and output of the data to the memory means (32) and also to the selection means (36), and for supplying as well the R/W signal to the input and output circuit (42).
Inventors
- 👤 Mitsuo Saito
- 👤 Takeshi Aikawa
- 👤 Akio Mori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 14:43
CPC Classifications
G; G11; G11C; G11C8/00; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G11C7/00; G11C7/10; G11C7/1006; G11C8/12
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
79 words
A memory device (30) for writing and reading data, characterised by: memory means (32) constructed so as to dispersedly memorize data with a plurality of bits; and control means (34,36,42,51,38,40,46,48) for driving said memory means so as to gain access at one time to data with a desired number of bits in order to write and read data with one kind of bit number among data having at least two kinds of bit number in said memory means (32).
Claim 2
Dependent Claim
79 words
A memory device (30) for writing and reading data, characterised by: memory means (32) constructed so as to dispersedly memorize data with a plurality of bits; and control means (34,36,42,51,38,40,46,48) for driving said memory means so as to gain access at one time to data with a desired number of bits in order to write and read data with one kind of bit number among data having at least two kinds of bit number in said memory means (32).
Claim 3
Dependent Claim
71 words
A memory device as claimed in claim 1, in which the control means comprises a selection means (36,46,48) for selectively supplying, in accordance with the desired bit number, to the memory means (32) address signals which designate a word made up of a plurality of bits in the memory means, and an indication means (38,40) for outputting to the memory means (32) an indication signal which designates the desired bit number.
Claim 4
Dependent Claim
79 words
A memory device as claimed in claim 2, in which the control means further comprises an input and output circuit (42) for controlling the input and output of data to and from the memory means (32) in accordance with an R/W signal, and a CPU (34) for supplying a bit width indication signal to the selection means (36) through an IO register (46) and for supplying as well an R/W signal (56) to the input and output circuit (42).
Claim 5
Dependent Claim
77 words
A memory device as claimed in claim 2, in which the memory means comprises a memory (32) which is constructed by a plurality of small memories to which the address signals are supplied in common, each memory being equipped independently with a data input and output line and a write and read control signal line, and the data with a plurality of bits that make up a word being memorized dispersedly at each of these small memories.
Claim 6
Dependent Claim
41 words
A memory device as claimed in claim 3, in which the selection means comprises a multiplexer (36) which receives the address signals and the bit width indication signal, and outputs selectively the address signal that corresponds to the desired bit number.
Claim 7
Dependent Claim
86 words
A memory device as claimed in claim 4, in which the selection means (36,46,48) outputs all of the address signals when access is made to the bits with the first bit number of the two kinds of bit number, and outputs a portion of the address signals when access is made to only the bits with the second bit number, and the indication means (38,40) receives the address signals that are not outputted from the selection means as a selection signal for the desired bit positions.
Claim 8
Dependent Claim
140 words
A memory device as claimed in claim 6, in which the indication means comprises a decoder (38) which receives the address signals that are not output from the selection means as a position selection signal when making access to the bits with the second bit number alone, and receives as well the bit width indication signal and outputs according to its address content, a write and record control signal to indicate the bits with the second bit number to the write and read control signal line in the memory, and a register (40) which, when making access to the bits with the first bit number, receives the bit width indication signal and outputs a write and read control signal to indicate the bits with the first bit number to the write and read control signal line in the memory (32).
Claim 9
Dependent Claim
37 words
A memory device as claimed in claim 7, in which the first bit number is the entire bit numbers in a word, and the second bit number is a portion of the bit numbers in a word.
Claim 10
Dependent Claim
76 words
A memory device as claimed in claim 8, in which the indication means further comprises a means which, when making access to a portion of bits in a word, supplies address signals for preventing the selection means from outputting signal to the input and output circuit (42) in order to let the input and output circuit (42) to output only the data corresponding to the portion of the bits through the data input and output line.
Claim 11
Dependent Claim
194 words
A memory device (30) for writing and reading data, characterised by: a memory (32) which is constructed by a plurality of small memories to which address signals are supplied commonly, each memory being equipped independently with a data input and output line and a write and read control signal line, and the data with a plurality of bits that make up a word being memorized dispersedly at each of these small memories; selection means (36,46,48) for supplying selectively in said memory means address signals which designate a word consisting of a plurality of bits, to said memory means (32) corresponding to the desired bit number among at least two kinds of bit numbers; indication means (38,40) for outputting an indication signal to designate the desired bit number in said memory means (32); an input and output circuit (42) for controlling the input and output of the data to said memory means (32) in accordance with an R/W signal (56); and a CPU (34) for supplying a bit width indication signal to said selection means through an 10 register (46), and for supplying as well an R/W signal to said input and output circuit (42).
Claim 12
Dependent Claim
194 words
A memory device (30) for writing and reading data, characterised by: a memory (32) which is constructed by a plurality of small memories to which address signals are supplied commonly, each memory being equipped independently with a data input and output line and a write and read control signal line, and the data with a plurality of bits that make up a word being memorized dispersedly at each of these small memories; selection means (36,46,48) for supplying selectively in said memory means address signals which designate a word consisting of a plurality of bits, to said memory means (32) corresponding to the desired bit number among at least two kinds of bit numbers; indication means (38,40) for outputting an indication signal to designate the desired bit number in said memory means (32); an input and output circuit (42) for controlling the input and output of the data to said memory means (32) in accordance with an R/W signal (56); and a CPU (34) for supplying a bit width indication signal to said selection means through an 10 register (46), and for supplying as well an R/W signal to said input and output circuit (42).
Claim 13
Dependent Claim
40 words
A memory device as claimed in claim 10, in which the selection means comprises a multiplexer (36) for receiving the address signals and the bit width indication signal, and for outputting selectively address signals corresponding to the desired bit number.
Claim 14
Dependent Claim
87 words
A memory device as claimed in claim 10, in which the selection means (36) outputs all of the address signals when access is desired to the bits with the first bit number of the two kinds of bit number, and outputs, when access is made to only the bits with the second bit number, a portion of the address signals, and the indication means (38,40) receives the address signals that are not outputted from the selection means (36) as a selection signal for the desired bit positions.
Claim 15
Dependent Claim
140 words
A memory device as claimed in claim 12, in which the indication means comprises a decoder (38) which, when making access to the bits with the second bit number alone, receives the address signals that are not outputted from the selection means (36), as a position selection signal, and receives as well the bit width indication signal and outputs, according to its address content, a write and read control signal to indicate the bits with the second bit number to the write and read control signal line in the memory, and a register (40) which, when making access to the bits with the first bit number, receives the bit width indication signal and outputs a write and read control signal to the write and read control signal line in the memory to indicate the bits with the first bit number.
Claim 16
Dependent Claim
37 words
A memory device as claimed in claim 13, in which the first bit number is the entire bit numbers in a word, and the second bit number is a portion of the bit numbers in a word.
Claim 17
Dependent Claim
77 words
A memory device as claimed in claim 14, in which the indication means further comprises a means which, when making access to a portion of bits in a word, supplies address signals for preventing the selection means (36) from outputting signal to the input and output circuit (42) in order to let the input and output circuit (42) to output only the data corresponding to the portion of the bits through the data input and output line.
Claim 18
Dependent Claim
18 words
An image display system characterised by a memory device according to any one of claims 1 to 15.
References Cited (Backward Citations)
No citation records indexed.
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