Patent US4786108A successfully refreshed from Google Patents.
Patent EP0155018A1 successfully refreshed from Google Patents.
EP0155018A1
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Arrangement of supervising the functions of a memory device
Assignee: Koninklijke Philips NV
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Filing: 1985-02-07
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Granted: —
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Expires: 2005-02-07
Abstract
Abstract For supervising the correct operation of a memory device it is proposed to divide this device into two or more modules (SRi). To that end the data words (DW) to be entered into the memory, each comprising a parity bit (PB), are divided into a like number of portions (SDWi) and each portion is entered into one of the modules (SRi). Checking the parity (PC) of associated portions (SDWi) of one data word (DW) then provides information on whether all portions have been addressed, entered, read etc. correctly.
Inventors
- 👤 Hans Hendrik Verheul
- 👤 Martinus Petrus Paulus De Wit
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 14:39
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1016; G06F11/1032
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
98 words
An arrangement for supervising the functions of a memory device for storing parity bit-containing data words, each having m bits, (m i 2), the arrangement comprising dividing means for dividing the data words into n (n ≥ 2) sub-data words, and the memory device comprising n separate sub-memory devices each coupled to the dividing means for storing a sub-data word in each of the n sub-memory devices, characterized in that the arrangement further comprises a parity checking device connected to the sub-memory devices for checking the parity of the n associated sub-data words which form one data word.
Claim 2
Dependent Claim
98 words
An arrangement for supervising the functions of a memory device for storing parity bit-containing data words, each having m bits, (m i 2), the arrangement comprising dividing means for dividing the data words into n (n ≥ 2) sub-data words, and the memory device comprising n separate sub-memory devices each coupled to the dividing means for storing a sub-data word in each of the n sub-memory devices, characterized in that the arrangement further comprises a parity checking device connected to the sub-memory devices for checking the parity of the n associated sub-data words which form one data word.
Claim 3
Dependent Claim
38 words
An arrangement for supervising the functions of a memory device as claimed in Claim 1, characterized in that the sub-datawords each contain m/n bits and that each memory location of the sub-memory devices can also contain m/n bits.
Claim 4
Dependent Claim
40 words
An arrangement for supervising the functions of a memory device as claimed in Claim 2, characterized in that the dividing means comprise a register having m bit positions and that the register has n outputs for the respective m/n-bit sub-datawords.
Claim 5
Dependent Claim
27 words
An arrangement for supervising the function of a memory device as claimed in Claim 1 or 2, characterized in that m = 12 and n = 3.
References Cited (Backward Citations)
US3972033A
Cited
EP0080354A2
Cited
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