Patent EP0154551A2 successfully refreshed from Google Patents.
EP0154551A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between said processors
Assignee: Motorola Solutions Inc
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Filing: 1985-03-06
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Granted: —
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Expires: 2005-03-06
Abstract
Abstract Apparatus is described for enabling a first processor to cause a second processor to effect a transfer of data between the processors in accordance with data transfer commands sent from the first processor to the second processor. The processors each have a program instruction memory for enabling the processors to operate independently and simultaneously when no data transfer is occurring between them. The apparatus comprises data transfer circuitry connected between the processors for enabling the data to be transferred. A program instruction decoder is associated with the second processor for normally decoding and executing instructions stored in the program instruction memory of the second processor when no data transfer is occurring. Routing circuitry carries the data transfer commands from the first processor to the program instruction decoder for decoding and executing to provide signals to the data transfer circuitry to effect a transfer of data.
Inventors
- 👤 Shahid U.H. Qureshi
- 👤 George P. Chamberlin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 11:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
156 words
1 . Apparatus adapted to enable a first processor to cause a second processor to effect a transfer of data between said processors in accordance with data transfer commands sent from said first processor to said second processor, said processors each having a program instruction memory adapted to enable said processors to operate independently and simultaneously when no data transfer is occurring between them, characterised in that said apparatus comprises: data transfer circuitry connected between said processors for enabling said data to be transferred; a program instruction decoder associated with said second processor and adapted normally to decode and to execute instructions stored in the program instruction memory of said second processor when no said data transfer is occurring; and routing circuitry adapted to carry said data transfer commands from said first processor to said program instruction decoder for decoding and execution to provide signals to said data transfer circuitry to effect said transfer of data.
Claim 2
Dependent Claim
156 words
1 . Apparatus adapted to enable a first processor to cause a second processor to effect a transfer of data between said processors in accordance with data transfer commands sent from said first processor to said second processor, said processors each having a program instruction memory adapted to enable said processors to operate independently and simultaneously when no data transfer is occurring between them, characterised in that said apparatus comprises: data transfer circuitry connected between said processors for enabling said data to be transferred; a program instruction decoder associated with said second processor and adapted normally to decode and to execute instructions stored in the program instruction memory of said second processor when no said data transfer is occurring; and routing circuitry adapted to carry said data transfer commands from said first processor to said program instruction decoder for decoding and execution to provide signals to said data transfer circuitry to effect said transfer of data.
Claim 3
Dependent Claim
47 words
Apparatus according to Claim 1,. further characterised in that said first processor further comprises an address bus for normally carrying addresses representing locations of instructions in the program instruction memory of said first processor, and said routing circuitry comprises at least a portion of said address bus.
Claim 4
Dependent Claim
49 words
Apparatus according to Claim 1 or Claim 2, further characterised in that data transferred from said first processor to said second processor specifies a task to be performed by said second processor by executing a set of corresponding instructions stored in the program instruction memory of said second processor.
Claim 5
Dependent Claim
35 words
Apparatus according to any preceding claim, further characterised in that it comprises circuitry for accepting from an information-carrying channel and delivering to said channel a carrier modulated in accordance with a sequence of signal points.
Claim 6
Dependent Claim
25 words
Apparatus according to Claim 4, further characterised in that said transferred data comprises information about said signal points sent and signals received over said channel.
Claim 7
Dependent Claim
26 words
Apparatus according to Claim 4 or Claim 5, further characterised in that said second processor is arranged to perform signal processing tasks on said received signals.
Claim 8
Dependent Claim
114 words
Apparatus according to any preceding claim, further characterised in that said second processor includes a memory adapted to store at successive addresses a number (M) of related pieces of said data upon which an operation is to be performed, in that said second processor includes an indirect address register adapted to hold a value corresponding to the address of the next one of said related pieces of information on which said operation is to be performed, and in that updating circuitry is provided, said circuitry being adapted for incrementing said value once after each performance of said operation until said incrementing has occurred M-1 times, and thereafter returning said value to its original level.
References Cited (Backward Citations)
No citation records indexed.
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