Integrated circuit chip assembly

Claim 2

Device comprising a substrate and at least one integrated circuit chip attached to said substrate, CHARACTERIZED IN THAT said substrate consists essentially of a single-crystal material, and said at least one circuit chip being electrically connected to lithographically defined electrical circuitry on said substrate.

Claim 3

Device according to claim 1, CHARACTERIZED IN THAT the material of at least a body portion of said substrate and the material of at least a body portion of said at least one chip have the same crystallographic structure.

Claim 4

Device according to claim 2, CHARACTERIZED IN THAT the material of said body portion of said substrate is essentially the same as the material of said body portion of said at least one chip.

Claim 5

Device according to claim 1 or 2 or 3, CHARACTERIZED IN THAT said material is a semiconductor material.

Claim 6

Device according to claim 1 or 2 or 3 or 4, CHARACTERIZED IN THAT said material is essentially silicon.

Claim 7

Device according to any one of preceding claims 1-5, CHARACTERIZED IN THAT said single-crystal material of the substrate is silicon.

Claim 8

Device according to any one of preceding claims 1-6, CHARACTERIZED IN THAT said electrical, circuitry comprises a ground conductor and a power conductor and a decoupling capacitor is between said ground conductor and said power conductor.

Claim 9

Device according to claim 7, CHARACTERIZED IN THAT said decoupling capacitor is a metal-oxide-semiconductor capacitor.

Claim 10

Device according to claim 8, CHARACTERIZED IN THAT. said capacitor consists of said substrate, an oxide layer on said substrate, and a metallic layer on said oxide layer.

Claim 11

Device according to any one of preceding claims 1-9, CHARACTERIZED IN THAT said substrate has at least one surface depression (hereinafter referred to as "well") which has at least one sloping wall resulting from crystallographically anisotropic etching, said at least one chip has at least one beveled edge resulting from crystallographically anisotropic etching, and said at least one beveled edge and said at least one slope are in juxtaposition, whereby said at least one chip is positioned on said substrate.

Claim 12

Device according to claim 10, CHARACTERIZED IN THAT said at least one chip has a circuit-carrying side which faces into said at least one well in said wafer.

Claim 13

Device according to claim 11, CHARACTERIZED IN THAT contact is made to said circuit by at least one stripe conductor on a sidewall of said well.

Claim 14

Device according to any one of preceding claims 10-12, CHARACTERIZED BY comprising a plurality of chips, said chips being electrically interconnected by electrical conductors on said wafer.

Claim 15

Device according to claim 13, CHARACTERIZED IN THAT said electrical conductors are separated by a photodefinable polymer material.

Claim 16

Device according to any one of preceding claims 10-14, CHARACTERIZED BY comprising at least one passive component which is mounted on said at least on chip.

Claim 17

Device according to any one of preceding claims 10-15, CHARACTERIZED IN THAT at least one optical fiber terminates on said at least one chip.

Claim 18

Device according to any one of preceding claims 1-9, CHARACTERIZED BY comprising a wafer and at least one circuit-carrying chip, .the material of said wafer being essentially in single-crystal form, the material of said at least one chip being in essentially the same single-crystal form as the material of said wafer, said at least one chip having a first surface and at least one first sidewall forming a first angle with said first surface, said angle being less than 90 degrees as resulting from etching of the material of said at least one chip, -said wafer having a second surface and at least one second sidewall forming a second angle with said second surface, said second angle being essentially supplementary to said first angle as resulting from etching of the material of said wafer, said at least one chip being in alignment with respect to said wafer as a result of matching between said at least one first sidewall and said at least one second sidewall, said at least one chip carrying an integrated circuit and a planarizing layer overlying said circuit and at least a portion of said wafer, and electrical connection to said circuit being made by metallization which overlies said planarizing layer.

Claim 19

Device according to claim 17, CHARACTERIZED IN THAT the material of said planarizing layer is a photo-definable material.

Claim 20

Device according to claim 17, CHARACTERIZED BY comprising two or more planarizing layers and metallizations.

Claim 21

Device according to any one of preceding claims 1-9, CHARACTERIZED IN THAT said substrate is a wafer having top and bottom surfaces, said wafer having conductive terminal portions along the periphery thereof overlying said top surface, at least one chip mounted at least on the top surface of said wafer includes conductive elements in a central portion of its top surface, each mounted chip having at least one sloped edge extending from said central portion toward the top surface of said wafer, and a conductive pattern connects the elements of a mounted device to said terminal portions or to elements included on another mounted chip or to both, said pattern being disposed on the sloped edge(s) of each mounted chip and overlying the top surface of said wafer.

Claim 22

Device according to claim 20, CHARACTERIZED IN THAT said wafer includes additional conductive terminal portions along the periphery thereof overlying said bottom surface, at least one chip mounted on the bottom surface of said wafer, said at least one chip including conductive elements in a central portion of its unmounted surface, each bottom-surface-mounted chip having at least one sloped edge extending from its central portion toward the bottom surface of said wafer, and a conductive pattern connecting the conductive elements of a bottom-surface-mounted chip to said additional terminal portions or to elements included on another bottom-surface-mounted chip or to both, said pattern being disposed on the sloped edge(s) of each bottom-surface-mounted chip and overlying the planar bottom surface of said wafer.

Claim 23

Device according to claim 20 or 21, CHARACTERIZED IT THAT said at least one chip comprises a monocrystalline silicon chip the top and bottom surfaces of which lie in (100) crystalline planes.

Claim 24

Device according to claim 22, CHARACTERIZED IN THAT said at least one sloped edge lies in a (111) crystalline plane of said silicon chip.

Claim 25

Device according to any one of preceding claims 20-23, CHARACTERIZED IN THAT the instrumentality mounting each chip on said wafer comprises an adhesive layer interposed between each device and said wafer.

Claim 26

Device according to any one preceding claims 1-9, CHARACTERIZED BY substrate having a relatively large surface and provided with terminal pads, a plurality of semiconductor chips each having front and back surfaces with its back surface contacting the surface of said substrate and its front surface including a plurality of conductive pads which provide external connections to circuit elements within the chip, each chip having at least one sloping edge extending from its front surface to said substrate, and conductive paths extending from the conductor pads along the sloping edges of the chips and the surface of the substrate for interconnecting chips to one another and to the terminal pads on the substrate.

Claim 27

Device according to claim 25, CHARACTERIZED IN THAT said substrate is a wafer, said at least one chip includes conductive pads in a central region of one surface of said chip mounted on said wafer, and at least one sloped wall extends from the central region of said at least one mounted chip to one surface of said wafer, a conductive pattern, including peripherally disposed elements, on the one surface of said wafer and on said at least one sloped wall connects said pads to other device pads or to said elements or to both.

Claim 28

Device according to any one of preceding claims 1-9, CHARACTERIZED BY a wafer having planar top and bottom surfaces, said wafer having conductive terminal portions along the periphery thereof overlying said top surface, at least one chip mounted on the bottom surface of said wafer, said chip including in a central portion of its top surface conductive pads facing said wafer, a sloped-wall aperture formed through said wafer in registry with the central portion of each mounted chip, and a conductive pattern connecting the pads of a mounted chip to said terminal portions, said pattern being disposed on at least one of the sloped walls associated with a mounted chip and overlying the planar top surface of said wafer.

Claim 29

Device according to claim 27, CHARACTERIZED IN THAT the instrumentality mounting each chip on the bottom surface of said wafer comprises an adhesive layer disposed around at least a peripheral portion of the top surface of each chip.

Claim 30

Device according to any one of preceding claims 1-9, CHARACTERIZED BY a plurality of semiconductive chips, each having a plurality of conductive pads on a top surface for providing electrical connections to circuit elements in the chip, a cap member to one surface of which is bonded separately at least a portion of the top surface of each of the plurality of chips, the cap member including sloped-wall apertures to permit access to the conductive pads, and conductive paths overlying an opposite surface of the cap member and extending along the sloped side walls of the apertures for contacting the conductive pads and interconnecting the chips.