EP0154379A2 — Improved array arrangement for EEPROMS

Claim 1

Independent Claim 226 words

In a memory system of the EEPRCM type including a plurality of sections of rows and columns of memory cells forming a plurality of bytes of memory, each section including a writing circuit having two terminals for charging and discharging its associated cells by applying differential voltages thereto, each row in each section including one memory cell for each column in the section, each section the same number of rows and the same number of columns, each of the memory cells in the same row and column location in each section together comprising each byte of memory, the improvement comprising simplified selection means for each section connecting all of the memory cells in a selected row to one side (9) of the associated writing circuit and all of the memory cells of a selected column to the other side (8) of the associated writing circuit, each selection means including prevention means preventing the associated writing circuit from applying a charging or discharging differential voltage to any memory cell except that in both the selected row and the selected column, each said writing circuit being capable of changing information in an associated selected from a first state (dischatged) to a second state (charged) or vice versa while another writing circuit is making the same or a different change in the information stored in its associated selected cell.

Claim 2

Dependent Claim 226 words

In a memory system of the EEPRCM type including a plurality of sections of rows and columns of memory cells forming a plurality of bytes of memory, each section including a writing circuit having two terminals for charging and discharging its associated cells by applying differential voltages thereto, each row in each section including one memory cell for each column in the section, each section the same number of rows and the same number of columns, each of the memory cells in the same row and column location in each section together comprising each byte of memory, the improvement comprising simplified selection means for each section connecting all of the memory cells in a selected row to one side (9) of the associated writing circuit and all of the memory cells of a selected column to the other side (8) of the associated writing circuit, each selection means including prevention means preventing the associated writing circuit from applying a charging or discharging differential voltage to any memory cell except that in both the selected row and the selected column, each said writing circuit being capable of changing information in an associated selected from a first state (dischatged) to a second state (charged) or vice versa while another writing circuit is making the same or a different change in the information stored in its associated selected cell.

Claim 3

Dependent Claim 174 words

In a memory system of the EEPRCM type according to Claim 1, wherein each cell includes a floating gate field effect transistor (Q M ) and a conventional field effect transistor (Q D ), each transistor including a source, a gate and a drain, the source of said conventional transistor being connected to the drain of said floating gate field effect transistor, said selection means turning on said conventional transistor to connect the drain of said floating gate transistor to the other terminal of its associated writing circuit, characterized in that said selection means includes a separate row select transistor (Q G ) for each row connecting the gates of all of said floating gate field effect transistors (Q M ) in its row to said one output terminal (9) and a separate column select transistor (Q CD ) for each column connecting the drains of all of said conventional transistors (Q D ) in its column to said other output terminal (8), said column select transistors can- prising part of said prevention means.

Claim 4

Dependent Claim 133 words

3 . In a memory system of the EEPRCM type according to claim 2, wherein each said prevention means operates when its associated writing circuit is to change information in a selected cell from said first state (discharged) to said second state (charged) to apply ground potential from said other terminal of said writing circuit to the drain of the column select transistor associated with said selected cell and to apply a higher potential to the sources of the floating gate transistor of each of the other memory cells in the selected row to prevent any other memory cell in said row from being charged, said writing circuit applying charging potential to the gate of the floating gate transistor of the selected cell from said one terminal through the associated row select transistor.

Claim 5

Dependent Claim 115 words

In a memory system of the EEPRCM type according to claim 3, wherein each said prevention means operates when its associated writing circuit is to change information in a selected cell from said second state to said first state to apply discharging potential from said other terminal of said writing circuit to the drain of the column select transistor associated with said selected cell and to apply ground potential to the sources of the floating gate transistor of each of the memory cells in the selected row, said writing circuit applying ground potential to the gate of the floating gate transistor of the selected cell from said one terminal through the associated row select transistor.

Improved array arrangement for EEPROMS

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