Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device configurated by using a polycell technique, comprising various function circuits, a plurality of unit cells (11A, 11B, 11C,...) storing said various function circuits, a plurality of cell arrays (11-1, 11-2, 11-3,...) each of which is constructed by said unit cells, and wiring regions (12-1, 12-2, 12-3,...) each of which is formed between the two adjacent cell arrays (11-1, 11-2, 11-3,...), wherein input and output terminals of said various function circuits stored in said unit cells (11A, 11B, 11C,...) are connected by a wiring layer formed on each of said wiring regions utilizing the polycell technique, characterized by comprising a first metal wiring layer (L8 to Lll) which is formed on each of said wiring regions (12-1, 12-2,...) having one end connected to the input and output terminals of said various function circuits stored in said unit cells (llA, lIB, 11C,...), a second metal wiring layer (L12, L13) formed on each of said wiring regions (12-1, 12-2,...), an insulating layer formed between said first metal wiring layer (L8 to Lll) and said second metal wiring layer (L12, L13), and a contact region (30-1 to 30-5) for connecting the other end of said first metal wiring layer (L8 to Lll) and said second metal wiring layer (L12, L13).

Claim 3

A device according to claim 1, characterized in that said first and second metal wiring layers (L8 to L13) are formed of aluminum.

Claim 4

A semiconductor integrated circuit device configurated by using a polycell technique, comprising various function circuits, a plurality of unit cells (11A, 11B, 11C,...) storing said various function circuits, a plurality of cell arrays (11-1, 11-2, 11-3,...) each of which is constructed by said unit cells, and wiring regions (12-1, 12-2, 12-3,...) each of which is formed between the two adjacent cell arrays (11-1, 11-2, 11-3,...), wherein input and output terminals of said various function circuits stored in said unit cells (llA, 11B, 11C,...) are connected by a wiring layer formed on each of said wiring regions utilizing the polycell technique, characterized by comprising a first metal wiring layer (L8 to Lll) which is formed on each of said wiring regions (12-1, 12-2,...) having one end connected to the output terminal of said various function circuits stored in said unit cells (llA, 11B, 11C,...), an insulating layer formed on said first metal wiring layer (L8 to Lll), a contact region (30-1 to 30-5) for connecting the other end of said first metal wiring layer (L8 to Lll) and said second metal wiring layer (L12, L13), an insulating layer formed on each of said unit cells (11A, 11B, 11C,...) of said cell arrays (11-1, 11-2, 11-3,...); and a metal wiring layer (L4, L9) which is formed on said insulating layer across said cell arrays (11-1, 11-2, 11-3,...).

Claim 5

A semiconductor integrated circuit device configurated by using a polycell technique, comprising various function circuits, a plurality of unit cells (11A, 11B, 11C,...) storing said various function circuits, a plurality of cell arrays (11-1, 11-2, 11-3,...) each of which is constructed by said unit cells, and wiring regions (12-1, 12-2, 12-3,...) each of which is formed between the two adjacent cell arrays (11-1, 11-2, 11-3,...), wherein input and output terminals of said various function circuits stored in said unit cells (llA, 11B, 11C,...) are connected by a wiring layer formed on each of said wiring regions utilizing the polycell technique, characterized by comprising a first metal wiring layer (L8 to Lll) which is formed on each of said wiring regions (12-1, 12-2,...) having one end connected to the output terminal of said various function circuits stored in said unit cells (llA, 11B, 11C,...), an insulating layer formed on said first metal wiring layer (L8 to Lll), a contact region (30-1 to 30-5) for connecting the other end of said first metal wiring layer (L8 to Lll) and said second metal wiring layer (L12, L13), an insulating layer formed on each of said unit cells (11A, 11B, 11C,...) of said cell arrays (11-1, 11-2, 11-3,...); and a metal wiring layer (L4, L9) which is formed on said insulating layer across said cell arrays (11-1, 11-2, 11-3,...).

Claim 6

A device according to claim 3, characterized in that said first and second metal wiring layers (Ll, L2, L5) and said metal wiring layer (L4) formed across said cell arrays (11-1, 11-2, 11-3,...) are formed of aluminum.

Claim 7

A semiconductor integrated circuit device configurated by using a polycell technique, comprising various function circuits having at least one gate electrode, a plurality of unit cells (11A, 11B, 11C,...) storing said various function circuits, a plurality of cell arrays (11-1, 11-2, 11-3,...) each of which is constructed by said unit cells, and wiring regions (12-1, 12-2, 12-3,...) each of which is formed between the two adjacent cell arrays (11-1, 11-2, 11-3,...), wherein input and output terminals of said various function circuits stbred in said unit cells (11A, 11B, 11C,...) are connected by a wiring layer formed on each of said wiring regions utilizing the polycell technique, characterized by comprising a first metal wiring layer (L8 to Lll) which is formed on each of said wiring regions (12-1, 12-2,...) having one end connected to the output terminals of said various function circuits stored in said unit cells (llA, 11B, 11C,...), a wiring layer which is formed on each of said wiring regions (12-1, 12-2,...) and extends to at least one said gate electrode of said various function circuits, a second metal wiring layer insulated from said first metal wiring layer and said wiring layer, and a contact region for connecting the other end of said first metal wiring layer with said wiring layer by means of said second metal layer.

Claim 8

A semiconductor integrated circuit device configurated by using a polycell technique, comprising various function circuits having at least one gate electrode, a plurality of unit cells (11A, 11B, 11C,...) storing said various function circuits, a plurality of cell arrays (11-1, 11-2, 11-3,...) each of which is constructed by said unit cells, and wiring regions (12-1, 12-2, 12-3,...) each of which is formed between the two adjacent cell arrays (11-1, 11-2, 11-3,...), wherein input and output terminals of said various function circuits stbred in said unit cells (11A, 11B, 11C,...) are connected by a wiring layer formed on each of said wiring regions utilizing the polycell technique, characterized by comprising a first metal wiring layer (L8 to Lll) which is formed on each of said wiring regions (12-1, 12-2,...) having one end connected to the output terminals of said various function circuits stored in said unit cells (llA, 11B, 11C,...), a wiring layer which is formed on each of said wiring regions (12-1, 12-2,...) and extends to at least one said gate electrode of said various function circuits, a second metal wiring layer insulated from said first metal wiring layer and said wiring layer, and a contact region for connecting the other end of said first metal wiring layer with said wiring layer by means of said second metal layer.

Claim 9

A device according to claim 5, characterized in that said first wiring layer serves to connect an output terminal provided in each of said unit cells (11A, 11B, 11C,...) and other wiring layers outside said unit cells (11A, 11B, 11C,...).

Claim 10

A device according to claim 5, characterized in that said first wiring layer extends onto said unit cells (llA, 11B, 11C,...)

Claim 11

A device according to claim 5, characterized in that said gate electrode is formed of polysilicon.

Claim 12

A device according to claim 5, characterized in that said second wiring layer serves to connect the input terminal in each of said unit cells and other metal wiring layers outside said unit cells (11A, 11B, 11C,...).

Claim 13

A semiconductor integrated circuit device configurated by using a polycell technique, comprising a semiconductor substrate (56) having a major surface, a well region (57) formed on the major surface of said semiconductor substrate (56), various function circuits formed on said well region (57) and said semiconductor substrate (56), a gate electrode (43A, 43B) formed over said well region (57) and said semiconductor substrate (56) through an insulating layer, characterized by comprising a first metal wiring layer (52) formed on an insulating layer, and a second metal wiring layer (54) formed on said first metal wiring layer (52) through an insulating layer, wherein said second metal wiring layer (54) is connected to said first metal wiring layer (52) and the latter to said gate electrode (43A) through contact holes formed in each of the insulating layers in the vicinity of a boundary between said semiconductor substrate and a side end portion of said well region (57).

Claim 14

A semiconductor integrated circuit device configurated by using a polycell technique, comprising a semiconductor substrate (56) having a major surface, a well region (57) formed on the major surface of said semiconductor substrate (56), various function circuits formed on said well region (57) and said semiconductor substrate (56), a gate electrode (43A, 43B) formed over said well region (57) and said semiconductor substrate (56) through an insulating layer, characterized by comprising a first metal wiring layer (52) formed on an insulating layer, and a second metal wiring layer (54) formed on said first metal wiring layer (52) through an insulating layer, wherein said second metal wiring layer (54) is connected to said first metal wiring layer (52) and the latter to said gate electrode (43A) through contact holes formed in each of the insulating layers in the vicinity of a boundary between said semiconductor substrate and a side end portion of said well region (57).

Claim 15

A device according to claim 10, characterized in that said first metal wiring layer is formed between said gate electrode (43A, 43B) and said second metal wiring layer, thereby connecting said gate electrode (43A, 43B) and said second metal wiring layer.

Claim 16

A device according to claim 10, characterized in that the contact hole (55) for connecting said gate electrode (43A) and said first metal wiring layer (52) and the contact hole (53) for connecting said first and second metal wiring layers (52, 54) are formed on the same gate electrode near the boundary between the side end portion of said well region (57) and said semiconductor substrate (57).

Claim 17

A device according to claim 10, characterized in that a contact between said gate electrode (43A) and said first metal wiring layer (52) and a contact between said first and second metal wiring layers (521.54) are performed through respective contact holes (53, 55) having positions coinciding along a vertical direction with respect to the major surface of said semiconductor substrate (56).

Claim 18

A device according to claim 10, characterized in that a distance between the side end portion of said well region (57) and an edge of the contact hole is shorter than a value obtained by adding a distance between the side end portion of said well region (57) and a prospective region for forming source and drain regions and said gate electrode (43A) to a value twice the width required for connecting said first and second metal layers (52, 54) and said gate electrode (43A).