Patent EP0154337A2 successfully refreshed from Google Patents.
EP0154337A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Transistor circuit for semiconductor device with hysteresis operation and manufacturing method therefor
Assignee: Toshiba Corp
•
Filing: 1985-03-06
•
Granted: —
•
Expires: 2005-03-06
Abstract
Abstract A transistor circuit with hysteresis operation, which is formed with a detector part (71, 72) and selector part (73, 74). The detector part (71, 72) detects a change in the level of an input signal (Vin) according to one of first and second threshold levels (V1, V2), and generates an output signal (Vout) having a level corresponding to the input signal (Vin). The level of the input signal (Vin) is changed between a first level (H) and a second level (L) which is lower than the first level (H). The first and second threshold levels (V1, V2) fall within a range defined between the first and second levels (H, L). The selector part (73, 74) selects one of the first and second threshold levels (V1, V2) in accordance with the level of the output signal (Vout), and applies the selected one threshold level (V1 or V2) to the detector part (71, 72).
Inventors
- 👤 Hiroshi C/O Patent Division Yasuda
- 👤 Kiyofumi C/O Patent Division Ochii
- 👤 Fujio C/O Patent Division Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 20:01
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
154 words
A transistor circuit for a semiconductor device with hysteresis operation, comprising: detector means (71, 72) for detecting a change in the level of an input signal (Vin) according to one of first and second threshold levels (V1, V2) and generating an output signal (Vout) having a level corresponding to said input signal (Vin), the level of said input signal (Vin) being changed between a first level (H) and a second level (L) which is different from said first level ( H ), and said first and second threshold levels (V1, V2) falling within a range defined between said first and second levels (H, L); and selector means (73, 74) coupled to said detector means (71, 72) for selecting one of said first and seocnd threshold levels (V1, V2) in accordance with the level of said output signal (Vout) and applying the selected one threshold level (V1 or V2) to said detector means (71, 72).
Claim 2
Dependent Claim
154 words
A transistor circuit for a semiconductor device with hysteresis operation, comprising: detector means (71, 72) for detecting a change in the level of an input signal (Vin) according to one of first and second threshold levels (V1, V2) and generating an output signal (Vout) having a level corresponding to said input signal (Vin), the level of said input signal (Vin) being changed between a first level (H) and a second level (L) which is different from said first level ( H ), and said first and second threshold levels (V1, V2) falling within a range defined between said first and second levels (H, L); and selector means (73, 74) coupled to said detector means (71, 72) for selecting one of said first and seocnd threshold levels (V1, V2) in accordance with the level of said output signal (Vout) and applying the selected one threshold level (V1 or V2) to said detector means (71, 72).
Claim 3
Dependent Claim
66 words
A transistor circuit according to claim 1, characterized in that said selector means (73, 74) applies the first threshold level (V1) to said detector means (71, 72) when the level of said output signal (Vout) represents said second level (L), and applies the second threshold level (V2) to said detector means (71, 72) when the level of said output signal (Vout) represents said first level (H).
Claim 4
Dependent Claim
46 words
A transistor circuit according to claim 1, characterized in that the difference (AVTH) between said first and second threshold levels (V1, V2) is so selected that said detector means (71, 72) is insensitive to variations in the potential of said input signal (Vin) due to noises.
Claim 5
Dependent Claim
41 words
A transistor circuit according to claim 1, characterized in that said first threshold level (V1) is used for detecting a signal transition that the level of said input signal (Vin) changes from the first level (H) to the second level (L).
Claim 6
Dependent Claim
41 words
A transistor circuit according to claim 4, characterized in that said second threshold level (V2) is used for detecting a signal transition that the level of said input signal (Vin) changes from the second level (L) to the first level (H).
Claim 7
Dependent Claim
100 words
A transistor circuit according to claim 1, characterized in that said detector means (71, 72) includes: a first transistor (71) having a source coupled to a power supply line (50), a gate responsive to said input signal (Vin) and a drain providing said output signal (Vout); and a second transistor (72) having a drain coupled to the drain of said first transistor (71), a gate responsive to said input signal (Vin) and a source resopnsive to a given potential (VB) for determining which of said first and second threshold levels (V1, V2) is applied to said detector means (71, 72).
Claim 8
Dependent Claim
82 words
A transistor circuit according to claim 6, characterized in that said selector means (73, 74) includes: a third transistor (73) having a drain coupled to the source of said second transistor (72), a gate responsive to said input signal (Vin) and a source coupled to another power supply line (GND); and a fourth transistor (74) having a drain coupled to still another power supply line (50), a gate responsive to said output signal (Vout) and a source providing said given potential (VB).
Claim 9
Dependent Claim
161 words
A transistor circuit according to claim 1, characterized in that said detector means (71, 72) includes: a first transistor (72) having a gate responsive to said input signal (Vin), a drain providing said output signal (Vout) and a source responsive to a given potential (VB) for determining which of said first and second threshold levels (VI, V2) is applied to said detector means (71, 72): and a load element (71A) coupled between a power supply line (50) and the drain of said first transistor (72), and characterized in that said selector means (73, 74) includes: a second transistor (73) having a drain coupled to the source of said first transistor (72), a gate responsive to said input signal (Vin) and a source coupled to another power supply line (GND); and a third transistor (74) having a drain coupled to still another power supply line (50), a gate responsive to said output signal (Vout) and a source providing said given potential (VB).
Claim 10
Dependent Claim
75 words
A transistor circuit according to claim 7, characterized in that said detector means (71, 72) further includes a switch element (71B) coupled between said power supply line (50) and said another power supply line (GND) and being responsive to a given signal ( CE ), for cutting-off a current path formed between said power supply line (50) and said another power supply line (GND) in accordance with the logical level of said given signal (CE).
Claim 11
Dependent Claim
20 words
A transistor circuit according to claim 7, characterized in that said first to fourth transistors (71-74) are enhancement MOS transistors.
Claim 12
Dependent Claim
40 words
A transistor circuit according to claim 7, characterized in that said first, third and fourth transistors (71, 73, 74) are enhancement MOS transistors, and said second transistor (72A) is an intrinsic MOS transistor whose gate threshold voltage is substantially zero.
Claim 13
Dependent Claim
20 words
A transistor circuit according to claim 11, which is used for converting a TTL level into a MOS logic level.
Claim 14
Dependent Claim
177 words
A transistor circuit according to claim 1, characterized in that said detector means (71, 72B) includes: a first transistor (71) having a source coupled to a power supply line (50), a gate responsive to said input signal (Vin) and a drain providing said output signal (Vout); and a second transistor (72B) having a drain coupled to the drain of said first transistor (71), a gate receiving a given bias potential and a source resopnsive to a given potential (VB) for determining which of said first and second threshold levels (VI, V2) is applied to said detector means (71, 72B), and characterized in that said selector means (73, 74) includes: a third transistor (73) having a drain coupled to the source of said second transistor (72B), a gate responsive to said input signal (Vin) and a source coupled to another power supply line (GND); and a fourth transistor (74) having a drain coupled to still another power supply line (50), a gate responsive to said output signal ( V out) and a source providing said given potential (VB).
Claim 15
Dependent Claim
23 words
A transistor circuit according to claim 13, characterized in that said first to fourth transistors (71, 728, 73, 74) are enhancement MOS transistors.
Claim 16
Dependent Claim
20 words
A transistor circuit according to claim 14, which is used for converting a TTL level into a MOS logic level.
Claim 17
Dependent Claim
227 words
A transistor circuit according to claim 1, characterized in that said selector means (73A, 74A, 73B, 74B) includes: a first PMOS transistor (73A) having a source coupled to a first positive power source (50),_a gate responsive to said input signal (Vin) and a drain; a second PMOS transistor (74A) having a drain coupled to a first negative power supply source (GND), a gate responsive to said output signal (Vout) and a source coupled to the drain of said first PMOS transistor (73A); a first NMOS transistor (738) having a source coupled to a second negative power source (GND), a gate responsive to said input signal (Vin) and a drain; and a second NMOS transistor (74B) having a drain coupled to a second positive power supply source (50), a gate responsive to said output signal (Vout) and a source coupled to the drain of said first NMOS transistor (73B); and characterized in that said detector means (72C, 72D) includes: a third PMOS transistor (72C) having a source coupled to the drain of said first PMOS transistor (73A), a gate responsive to said input signal (Vin) and a drain providing said output signal (Vout); and a third NMOS transistor (72D) having a source coupled to the drain of said first NMOS transistor (73B), a gate responsive to said input signal (Vin) and a drain providing said output signal (Vout).
Claim 18
Dependent Claim
33 words
A transistor circuit according to claim 16, characterized in that said first to third PMOS transistors (73A, 74A, 72C) and said first to third PMOS transistors (73B, 74B, 72D) are enhancement MOS transistors.
Claim 19
Dependent Claim
48 words
A transistor circuit according to claim 7, characterized in that said detector means (71, 72) further includes an inverter (15, 16) responsive to another input signal (Vin), for inverting the phase of said another input signal and providing a phase-inverted signal which serves as said input signal (Vin).
Claim 20
Dependent Claim
123 words
A transistor circuit according to claim 1, characterized in that said detector means (71, 72) includes: a first inverter (15X, 16X) responsive to another input signal ( V in), for inverting the phase of said another input signal and providing a phase-inverted signal; and a second inverter (71X, 72X) coupled to said first inverter (15X, 16X), for inverting the phase of said phase-inverted signal and providing said output signal (Vout), and characterized in that said selector means (73, 74) includes: a third inverter (74X) coupled to said second inverter (71X, 72X), for inverting the phase of said output signal (Vout) and supplying a phase-inverted output signal which is supplied to a coupling node between said first and second inverters (15X, 16X; 71X, 72X).
Claim 21
Dependent Claim
38 words
A transistor circuit according to claim 1, characterized in that said transistor circuit is adapted to an address transition detector circuit, and said output signal (Vout) is used as an input signal of said address transition detector circuit.
Claim 22
Independent Claim
185 words
A method for manufacturing a semiconductor device, comprising the steps of: a) effecting a gate oxidation on a surface of a first conductivity (p) type semiconductor substrate (110) which is surrounded by a field oxide layer (120), and forming a gate oxide film (130) with a predetermined thickness; b) implanting ions having said first conductivity (p) type into said substrate (110) by means of a deep implantation with a given acceleration voltage and with a given dose; c) forming a resist film (140) at a given surface region (B) on said gate oxide film (130); d) implanting an impurity of said first conductivity (p) type into said substrate (110) by means of a shallow implantation with a relatively low acceleration voltage and with a relatively low dose; e) removing said film (140); f) forming polycrystalline silicon layers (150A, 150B) at prescribed positions on said gate oxide film (130); and g) implanting an impurity of a second conductivity (n) type into said substrate (110), each of said polycrystalline silicon layers (150A, 150B) serving as a mask during the implantation of said second conductivity (n) type impurity.
Claim 23
Independent Claim
185 words
A method for manufacturing a semiconductor device, comprising the steps of: a) effecting a gate oxidation on a surface of a first conductivity (p) type semiconductor substrate (110) which is surrounded by a field oxide layer (120), and forming a gate oxide film (130) with a predetermined thickness; b) implanting ions having said first conductivity (p) type into said substrate (110) by means of a deep implantation with a given acceleration voltage and with a given dose; c) forming a resist film (140) at a given surface region (B) on said gate oxide film (130); d) implanting an impurity of said first conductivity (p) type into said substrate (110) by means of a shallow implantation with a relatively low acceleration voltage and with a relatively low dose; e) removing said film (140); f) forming polycrystalline silicon layers (150A, 150B) at prescribed positions on said gate oxide film (130); and g) implanting an impurity of a second conductivity (n) type into said substrate (110), each of said polycrystalline silicon layers (150A, 150B) serving as a mask during the implantation of said second conductivity (n) type impurity.
Claim 24
Independent Claim
185 words
A method for manufacturing a semiconductor device, comprising the steps of: a) effecting a gate oxidation on a surface of a first conductivity (p) type semiconductor substrate (110) which is surrounded by a field oxide layer (120), and forming a gate oxide film (130) with a predetermined thickness; b) forming a resist film (140) at a given surface region (B) on said gate oxide film (130); c) implanting an impurity of said first conductivity (p) type into said substrate (110) by means of a shallow implantation with a relatively low acceleration voltage and with a relatively low dose; d) removing said film (140); e) implanting ions having said first conductivity (p) type into said substrate (110) by means of a deep implantation with a given acceleration voltage and with a given dose; f) forming polycrystalline silicon layers (150A, 150B) at prescribed positions on said gate oxide film (130); and g) implanting an impurity of a second conductivity (n) type into said substrate (110), each of said polycrystalline silicon layers (150A, 150B) serving as a mask during the implantation of said second conductivity (n) type impurity.
Claim 25
Independent Claim
185 words
A method for manufacturing a semiconductor device, comprising the steps of: a) effecting a gate oxidation on a surface of a first conductivity (p) type semiconductor substrate (110) which is surrounded by a field oxide layer (120), and forming a gate oxide film (130) with a predetermined thickness; b) forming a resist film (140) at a given surface region (B) on said gate oxide film (130); c) implanting an impurity of said first conductivity (p) type into said substrate (110) by means of a shallow implantation with a relatively low acceleration voltage and with a relatively low dose; d) removing said film (140); e) implanting ions having said first conductivity (p) type into said substrate (110) by means of a deep implantation with a given acceleration voltage and with a given dose; f) forming polycrystalline silicon layers (150A, 150B) at prescribed positions on said gate oxide film (130); and g) implanting an impurity of a second conductivity (n) type into said substrate (110), each of said polycrystalline silicon layers (150A, 150B) serving as a mask during the implantation of said second conductivity (n) type impurity.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.