Device for speaker verification

Claim 2

Device for speaker's verification comprising a circuit (EP) extracting characteristic parameters of each sentence, the parameters being energy values associated with speech signal in different frequency bands of the speech band and vector components each related to an interval of the useful time for sentence pronounciation, a circuit (DP) calculating the vector average which supplies an average parameter vector, a circuit determining histograms, one for each frequency band, of distribution of the average parameters on many repetitions of the same sentence, a memory (MEM) of the histograms of each speaker, a circuit (CP) calculating the probability that a sentence just spoken belongs to a given speaker, a circuit (CSV) calculating the probability threshold, and a comparison circuit (CMP) which emits a signal of speaker verified if the probability overcomes the probability threshold value, characterized by the fact that it comprises also: - a circuit (RIF) determining the real instants of sentence beginning and end upstream the circuit (EP) extracting the characteristic parameters, which circuit (RIF) calculates at each interval a long-term power value of the speech signal, long-term indicating a period of a certain number of consecutive intervals, calculates at each interval a short-term weighted power value, short-term being an interval period, obtained as the power product of the speech signal by the ratio between a speech signal power at low frequencies and a speech signal power at high frequencies, compares the long-term power values incremented by a fixed quantity with the short-term weighted power and considers the instant where the second value exceeds the first values as the real instant of sentence beginning if this condition is. always verified for a certain number of consecutive intervals (FRAGB, FRAGE) after this instant, repeats these operations for determining the real instant of sentence end analyzing the intervals from the last sentence interval backwards and supplies the parameter extraction circuit (EP) only with the intervals comprised between the real instants of sentence beginning and end; - a time alignment circuit (AT), downstream the parameter extraction circuit (EP), which circuit (AT) determines a correspondence table, then called alignment path (at,Fig. 2), between indexes of vector parameters supplied by the parameter extraction circuit and parameter vectors of a reference sentence, and according to this table it generates a new sequence of aligned parameter vectors whose number corresponds to that of parameter vectors of reference sentence, the vectors of aligned parameters being sent to said average calculating circuit (DP); being also characterized by the fact that the circuit (CSV) calculating the probability threshold comprises a circuit (CDEV) calculating the product of standard deviations of the distribution histograms of average parameters, said probability threshold being then divided by a corrective factor consisting essentially of the product of standard deviations, obtaining a variable probability threshold.

Claim 3

Device as in claim 1, comprising a digital converter (AD) of the speech signal for all the time useful for sentence pronounciation, which obtains a set of digital samples to be written in a memory of digital samples (MMl), characterized by the fact that the circuit (RIF) determining the real instants of sentence beginning and end consists of: - a frequency divider (OFR) which divides the sampling frequency of the converter (AD) for the division into time intervals, each interval comprising a certain number of digital samples; - a delay circuit (Tl) of a number DN of intervals for the digital samples; - a circuit (PLT) calculating the long-term power associated with the samples received from the delay circuit (Tl), and at each interval the logarithm of the mean of the squares of the values received in the last NFN intervals; - a first register (RG1) which receives the long-term power values and emits them when it is enabled by a first enabling signal (22) consisting of the output signal of the frequency divider (OFR) sent through logic gates (34, 35, 37); - a first adder (Sl) of the output of the first register (RG1) and a constant value (ST01), which sends the result to a second register (RG2) also enabled by the first enabling signal (22); - a circuit calculating the short-term weighted power which consists of a first (PBT1), a second (PBT2) and a third (PBT3) circuit calculating the short-term power which evaluate, at each interval, the logarithm of the mean of the squares of the values received in the last interval, the first circuit (PBT1) receiving the samples, the second circuit (PBT2) the samples filtered in a low-pass filter (FPB), the third circuit ( PBT3) the samples filtered in a high-pass filter (FPA), the third circuit output being subtracted from the second circuit output in a subtractor (S2) whose output is added to that of the first circuit (PBT1) in a second adder (S3); - a third register (RG3) which receives the second adder (S3) output and is enabled by a second enabling signal (43) consisting of the output signal of the frequency divider (OFR) sent through a logic gate (42); - a programmable up-down counter (CT1) which counts the intervals, i.e. the periods of the output signal of the frequency divider (OFR), the counter counting up starting from zero during the research of the sentence beginning point, and counting down starting from a maximum interval value during the research of the sentence end point; - a fourth register (RG4) which stores the value of the counter (CT1) output when a third enabling signal (33) is received; - a second counter (CT3), reset by the third enabling signal (33), which counts the periods of the output signal of the frequency divider (OFR), said signal being sent through a logic gate (47) enabled by the third enabling signal (33); - a first comparator (CMP5) which compares the second counter (CT3) output with a constant value consisting of said number of consecutive intervals (FRAGE, FRAGB) and emits an acknownledgment signal (51) when the second counter (CT3) output exceeds the constant value; - a second comparator (CMP1) which compares the outputs of the third (RG3) and second (RG2) register and, when third register output exceeds second register output, it emits said third enabling signal (33) also sent as inhibiting signal to said logic gates (34, 37) which generate the first enabling signal (22); 1 - a third comparator (CMP2) which, when the up/down counter (CT1) output exceeds a constant value (ST06), emits an enabling signal (41) for the logic gate (42) which generates the second enabling signal (43); - a control logic (LC) which, upon reception of a control signal (PU), determines the increasing sequential reading of the digital sample memory (MM1) and the beginning of up counting of said up/down counter (CT1), and upon reception of the acknowledgement signal (51), considers the fourth register (RG4) output value as the real instant of sentence beginning, emits the down counting signal towards the counter (CT1) and determines the decreasing sequential reading of the digital sample memory (MM1) and upon reception of the acknowledgement signal (51) considers the fourth register (RG4) output as the real instant of sentence end.

Claim 4

Device as in claim 2, characterized by the- fact that the circuit determining the real instant (RIF) consists also of: - a third counter (CT3), reset by the third enabling signal (33), which counts the periods of output signal of the frequency divider (OFR), said signal being sent through the logic gate (47) enabled by the third enabling signal (33); - a fourth comparator (CMP4) which compares the third counter (CT3) output with a constant value, and as far as the constant value is not exceeded, emits a signal (36) which keeps the enablement for the logic gates (34, 35, 37) which emit the first enabling signal (22), after the second comparator (CMPI) has supplied the inhibition signal (33); - a fifth comparator (CMP3) which compares up/down counter (CT1) output with an interval threshold value, the threshold overcoming determining the emission of an error signal (44) towards the control logic which stops operations.

Claim 5

Device as in any of claims 1 to 3, characterized by the fact that said time alignment circuit (AT) consists of: - a first memory (MM2) containing the parameter vectors of the reference sentence, each vector being identified by an index m (1≤m≤M); - a second memory (MM5) where the extraction parameter circuit (EP) writes the parameter vectors just calculated of a sentence, each vector being identified by an index j (1≤j≤J); - a circuit (CBC) calculating directions which receives the vectors from the first and the second memory and, for each pair of indexes (j, m) of the vectors, calculates direction values P(j,m) which indicate from which previous pair of contiguous indexes (j,m-1; j-1,m; j-l,m-1) the minimum of the additions of differences between corresponding components of the vectors comes; . - a third memory (MEMP) which contains said direction values P(j,m) in positions where address is given by the values of the corresponding pairs of indexes j, m; - a first addressing and calculating logic (LAR, nr, pr, j, m) which subtracts from the present address the direction value P(j,m) read in the third memory (MEMP), and obtains next address for memory reading, starting from the position corresponding to the pair of indexes J, M; furthermore, it writes sequentially in a fourth memory (MEMC) the addresses generated, the addresses composing said alignment path (at); - a second addressing and calculating logic (ALTE), which addresses in a sequential increasing order the fourth memory (MEMC), reads the pairs of indexes j, m of alignment path (at), uses index j for reading addressing of second memory (MM5) and index m for writing addressing of a fifth memory (MEMM), and compares the values of present and previous index m: if present value exceeds previous value, it writes in the fifth memory the value read in the second memory, if present value is equal to previous value it calculates and writes in the fifth memory the average of all consecutive vectors, read in the second memory, whose index j is given by index pairs having present index m value, the fifth memory (MEMM) containing then the sequence of vectors of parameters aligned; - a logic (LGC) controlling the operation of time alignment circuit (AT).

Claim 6

Device as in claim 4, characterized by the fact that said circuit calculating directions (CBC) consists of two cascaded configurations of equal circuits, called cells (C(-R),...CO,...CR), identified by odd and even indexes r(-R<r<R), whose value is the difference between the indexes of vectors coming from said first (MM2) and second (MM5) memory, each cell comprising: - a fifth register (REG5) which receives from previous cell of the same configuration the vectors of parameters coming from second memory (MH5) and emits them towards the following cell of the same configuration; - a sixth register (REG6) which receives from the following cell of the same configuration the vectors of parameters coming from the first memory (MM2) and emits them towards the previous cell of the same configuration; - a distance calculation circuit (CDS) which calculates the addition of the differences between homologous components of the vectors present at the outputs of the fifth (REG5) and sixth (REG6) register; - a circuit calculating accumulated distances (CDA) which comprises: a comparator which verifies the minimum between three values consisting of a value of accumulated distance obtained at previous calculation and temporarily stored in a seventh register (REG7), values of accumulated distance present at the output of circuits calculating accumulated distances (CDA) of the two cells of contiguous index pertaining to the other cascaded configuration, and emits an indication related to the minimum value out of the three values, the indication being a direction value P(j,m); an adder of the distance value supplied by the distance calculation circuit (CDS) and the minimum of the three values, the adder emitting the accumulated distance values sent to the inputs of the corresponding circuits of the contiguous cells of the other cascaded configuration; - an enabling circuit (TFL) which enables the operation of the circuit calculating-accumulated distance (CDA) and of the seventh register (REG7) when it verifies the contemporary presence of data at fifth (REGS) and sixth (REG6) register outputs.

Claim 7

Device as in any of claims 1 to 5, characterized by the fact that the circuit (CSV) calculating the probability threshold consists of: - the circuit (CDEV) calculating the standard deviation of each speaker histogram received from histogram memory (MEM); - registers (R1,...RK), one for each histogram, which temporarily store the corresponding value of standard deviation supplied by the circuit (CDEV) calculating the standard deviation; - a circuit (PRD) calculating the product of the values present in said registers (R1,...RK); - a first divider (DVS1) which divides the values received from the circuit (PRD) calculating the product by a constant normalizing value (σ K NORM ); - a power raising circuit (ELP) which calculates the Z-th power and then the K-th root of the value received from the first divider (DVS1), where Z is a fixed exponential factor and K is the histogram number; - a second divider (DVS2) which divides the probability threshold by a value present at the output of the power raising circuit (ELP) obtaining the variable probability threshold; - a circuit (GSI) generating the control and synchronisation signals.