Logic circuit

Claim 2

A logic circuit comprising a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, an input terminal connected to a gate of said driver transistor, and a gate voltage generator which is connected to a gate of said load transistor and which generates a level higher than the sum of threshold values of said load transistor and said driver transistor and lower than a low value among the first sum of a built-in voltage of said load transistor and the threshold voltage of said driver transistor and the second sum of a built-in voltage of said driver transistor and the threshold voltage of said load transistor.

Claim 3

A logic circuit comprising a first inverter and a second inverter, said first inverter and said second inverter each comprising a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, and an input terminal connected to a gate of said driver transistor, and a gate voltage generator which is connected to a gate of said load transistor and which generates a level higher than the sum of threshold values of said load transistor and said driver transistor and lower than a low value among the first sum of a built-in voltage of said load transistor and the threshold voltage of said driver transistor and the second sum of a built-in voltage of said driver transistor and the threshold voltage of said load transistor.

Claim 4

A logic circuit comprising a first inverter and a second inverter, said first inverter and said second inverter each comprising a driver transistor and a load transistor formed by a junction type or Schottky barrier type field effect transistor, and an input terminal connected to a gate of said driver transistor, and a gate voltage generator which is connected to a gate of said load transistor and which generates a level higher than the sum of threshold values of said load transistor and said driver transistor and lower than a low value among the first sum of a built-in voltage of said load transistor and the threshold voltage of said driver transistor and the second sum of a built-in voltage of said driver transistor and the threshold voltage of said load transistor.

Claim 5

A logic circuit according to claim 1 or 2, wherein said gate voltage generator is formed by dividing an electric source voltage using two resistors.

Claim 6

A logic circuit according to claim 1 or 2, wherein said gate voltage generator is formed by connecting said gate of said load transistor to a common terminal.

Claim 7

A logic circuit according to claim 1 or 2, wherein said gate voltage generator comprises a series circuit of constant current electric sources) connected to an electric source voltage and a diode connected between said constant current electric sources and a common terminal, and the connecting point between said constant current electric sources and said diode is connected to said gate of said load transistor.

Claim 8

A logic circuit according -do claim 5, wherein said constant current source is formed by a depletion type field effect transistor in which a gate and a source is connected and said diode is formed by a junction type or Schottky barrier type field effect transistor in which a drain and a source is short circuited.

Claim 9

A bit line pull up circuit of a memory circuit comprising: bit lines and word lines, a memory cell provided at the cross point of the bit lines and the word line, said memory cell having a first and a second driver junction type or Schottky barrier type field effect transistors each having a source operatively connected to a common terminal, and a gate and a drain thereof being cross connected to each other, a first and" a second load each connected between the drain of said first and second driver field effect transistors and an electric source voltage, a first and a second transfer field effect transistors connected between the drain of said first and second driver transistors and said bit lines and having a gate connected to one of said word lines, a first and second bit line pull up transistor connected between one end of said bit lines and an electric source, a gate voltage generator which is connected to the gate of said first and second bit line pull up transistors and which generates a level higher than the sum of threshold values of said bit line pull up transistor and said driver transistor of the memory cell and lower than a low value among the first sum of a built-in voltage of said bit line pull up transistor and the threshold voltage of said driver transistor and the second sum of a built-in voltage of said driver transistor and the threshold voltage of said bit line pull up transistor.

Claim 10

A bit line pull up circuit of a memory circuit comprising: bit lines and word lines, a memory cell provided at the cross point of the bit lines and the word line, said memory cell having a first and a second driver junction type or Schottky barrier type field effect transistors each having a source operatively connected to a common terminal, and a gate and a drain thereof being cross connected to each other, a first and" a second load each connected between the drain of said first and second driver field effect transistors and an electric source voltage, a first and a second transfer field effect transistors connected between the drain of said first and second driver transistors and said bit lines and having a gate connected to one of said word lines, a first and second bit line pull up transistor connected between one end of said bit lines and an electric source, a gate voltage generator which is connected to the gate of said first and second bit line pull up transistors and which generates a level higher than the sum of threshold values of said bit line pull up transistor and said driver transistor of the memory cell and lower than a low value among the first sum of a built-in voltage of said bit line pull up transistor and the threshold voltage of said driver transistor and the second sum of a built-in voltage of said driver transistor and the threshold voltage of said bit line pull up transistor.