Patent EP0153015A2 successfully refreshed from Google Patents.
EP0153015A2
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EP
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Wafer scale integrated circuits
Assignee: STC PLC
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Filing: 1985-01-30
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Granted: —
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Expires: 2005-01-30
Abstract
Abstract A wafer scale integrated circuit comprises an array of similar circuit blocks (11 ), e.g. random access memory blocks, and a block recognition address bus (14) for storing an address code in each functional block. The blocks are coupled in a serial manner to the bus. An initial address is applied to the bus from a generator (13) and this address is stored in the first functional block. The address bus then augments this code to provide an address for the next functional block and so on.
Inventors
- 👤 Trevor Kenneth Monk
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 01:32
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0669; G06F12/0676
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
44 words
A wafer scale integrated circuit, including a plurality of similar circuit blocks, at least some of which are functional, and means for providing each said functional block with an address from a sequence of addresses and for storing that address in the functional block.
Claim 2
Dependent Claim
44 words
A wafer scale integrated circuit, including a plurality of similar circuit blocks, at least some of which are functional, and means for providing each said functional block with an address from a sequence of addresses and for storing that address in the functional block.
Claim 3
Dependent Claim
107 words
A wafer scale integrated circuit, including an array of blocks of memory cells, a block recognition address bus to which the memory blocks are coupled in a serial manner, an address generator adapted to apply an initial address code via the bus to the first memory block of the series, and a data bus whereby in use data are stored in and retrieved from the memory blocks, wherein the address bus has means one associated with each memory block for storing a block address in each functional memory block and for generating from that address a new address for the next functional memory block in the series.
Claim 4
Dependent Claim
107 words
A wafer scale integrated circuit, including an array of blocks of memory cells, a block recognition address bus to which the memory blocks are coupled in a serial manner, an address generator adapted to apply an initial address code via the bus to the first memory block of the series, and a data bus whereby in use data are stored in and retrieved from the memory blocks, wherein the address bus has means one associated with each memory block for storing a block address in each functional memory block and for generating from that address a new address for the next functional memory block in the series.
Claim 5
Dependent Claim
41 words
A wafer scale integrated circuit as claimed in claim 1, wherein said block recognition address bus includes adders one associated with each memory block whereby a new address is formed by augmentation of an address corresponding to a functional memory block.
Claim 6
Dependent Claim
33 words
A wafer scale integrated circuit as claimed in claim 1 or 2, wherein each said memory block has programmable means whereby its functionality or non- functionality may be indicated to the address bus.
Claim 7
Dependent Claim
23 words
An integrated circuit as claimed in any one of claims 1 to 4, wherein non-functional blocks are disabled from the circuit power supply.
Claim 8
Dependent Claim
15 words
A wafer scale integrated circuit substantially as described herein with reference to the accompanying drawings.
Claim 9
Dependent Claim
15 words
A wafer scale integrated circuit substantially as described herein with reference to the accompanying drawings.
Claim 10
Dependent Claim
20 words
A computer incorporating one or more wafer scale integrated circuits as claimed in any one of claims 1 to 6.
References Cited (Backward Citations)
No citation records indexed.
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