Patent EP0152625A2 successfully refreshed from Google Patents.
EP0152625A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of producing a semiconductor device comprising an active silicon region.
Assignee: Sony Corp
•
Filing: 1984-12-24
•
Granted: —
•
Expires: 2004-12-24
Abstract
Abstract A polycrystalline silicon layer is used to allow simultaneous fabrication of both N- and P-type MOSFET's on a common channel layer during integrated circuit fabrication. The polysilicon layer is between 20A and 750A thick, and preferably between 200A and 500A thick. These dimensions afford the polysilicon layer the high effective mobility, low threshold voltage and low leakage current characteristics, especially if the vapor-deposited polysilicon layer is annealed and/or ion implanted with Si + or Ge + after deposition. Application of the polysilicon layer over adjoining insulating and P-type semiconducting areas allows the single polysilicon layer to serve as active terminals and channels of both conductivity types of MOS transistors without intervening insulating or semiconducting layers. Deposition of the polysilicon layer in direct contact with a single-crystal substrate enhances the beneficial electrical properties of the polysilicon layer, especially if the polysilicon layer is annealed following deposition.
Inventors
- 👤 Hisao Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 17:56
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D62/00; H10D62/40; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D86/00; H10D86/201; H10D88/00
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
59 words
A polycrystalline silicon layer to be deposited on a semiconductor substrate applicable to semiconductor devices, characterised in that said polycrystalline silicon layer serves as an active region of the semiconductor device and has a thickness in a specific thickness range in which said polycrystalline silicon layer exhibits a sufficiently high effective carrier mobility and a sufficiently low threshold voltage.
Claim 2
Dependent Claim
59 words
A polycrystalline silicon layer to be deposited on a semiconductor substrate applicable to semiconductor devices, characterised in that said polycrystalline silicon layer serves as an active region of the semiconductor device and has a thickness in a specific thickness range in which said polycrystalline silicon layer exhibits a sufficiently high effective carrier mobility and a sufficiently low threshold voltage.
Claim 3
Dependent Claim
23 words
The polycrystalline silicon layer as set forth in claim 1, which is adapted for use in a field-effect transistor fabricated using thin-film technology.
Claim 4
Dependent Claim
20 words
The polycrystalline silicon layer as set forth 0 in claim 2, wherein said thickness range is from 100A to 750A.
Claim 5
Dependent Claim
20 words
The polycrystalline silicon layer as set forth in claim 3, wherein said thickness range is from 100A to a 600A.
Claim 6
Dependent Claim
21 words
The polycrystalline silicon layer as set forth 0 in claim 3, wherein said thickness range is from 200A to 0 500A.
Claim 7
Dependent Claim
48 words
The polycrystalline silicon layer as set forth in claim 3, which is formed by a process comprising the steps of: depositing polycrystalline silicon onto said semiconductor substrate to a thickness greater than that required in the finished device; and thermally oxidizing said layer to obtain the desired thickness.
Claim 8
Dependent Claim
30 words
The polycrystalline silicon layer as set forth in claim 1, wherein said layer is used in fabricating C-MOS inverters including MOS transistors which are formed on said polycrystalline silicon layer.
Claim 9
Dependent Claim
56 words
The polycrystalline silicon layer as set forth in claim 7, wherein said C-MOS inverter has a semiconductor substrate supporting a field SiO 2 layer, a first MOS transistor is formed on said substrate over said polycrystalline silicon layer and a second MOS transistor is formed on said field Si0 2 layer over said polycrystalline silicon layer.
Claim 10
Dependent Claim
49 words
The polycrystalline silicon layer as set forth in claim 8, wherein said polycrystalline silicon layer is formed on said substrate and field Si0 2 layer by a process comprising the step of depositing one of polycrystalline silicon and amorphous silicon immediately prior to forming said first and second transistors.
Claim 11
Dependent Claim
28 words
The polycrystalline silicon layer as set forth in claim 9, wherein the source and drain regions of said MOS transistors are both formed in said polycrystalline silicon layer.
Claim 12
Dependent Claim
43 words
ll. The polycrystalline silicon layer as set forth in claim 9, wherein said polycrystalline silicon layer forming process further includes the steps of implanting in said layer ions from the same family of elements of the periodic table and of annealing said layer.
Claim 13
Dependent Claim
70 words
A field effect transistor comprising: a semiconductor substrate; a polycrystalline silicon active layer formed on said substrate, said active layer having a thickness 0 0 in the range of 100A to 750A and forming therein a source region and a drain region; a gate electrode formed on said polycrystalline silicon layer over an insulating layer; and electrically conductive input/output terminals in contact with said source region and said drain region.
Claim 14
Dependent Claim
70 words
A field effect transistor comprising: a semiconductor substrate; a polycrystalline silicon active layer formed on said substrate, said active layer having a thickness 0 0 in the range of 100A to 750A and forming therein a source region and a drain region; a gate electrode formed on said polycrystalline silicon layer over an insulating layer; and electrically conductive input/output terminals in contact with said source region and said drain region.
Claim 15
Dependent Claim
23 words
The field effect transistor as set forth in claim 12, wherein the range of thickness of said active layer is 100A to 600A.
Claim 16
Dependent Claim
25 words
The field effect transistor as set forth in claim 12, wherein the range of thickness of said active o a layer is 200A to 500A.
Claim 17
Dependent Claim
59 words
The field effect transistor as set forth in claim 12, which is formed by a process comprising the steps of: depositing a layer of polycrystalline silicon onto said semiconductor substrate to a thickness greater than required for a finished device; and performing thermal oxidation of the polycrystalline silicon layer so as to reduce its thickness to the desired dimensions.
Claim 18
Dependent Claim
92 words
A process for fablicating a field effect transistor having a semiconductor substrate, a thin polycrystalline silicon film formed on said substrate, a gate electrode formed on said polycrystalline silicon film over an insulating layer, and input/output terminals connected to a source region and a drain region formed in said polycrystalline silicon film, said process comprising the steps of: depositing polycrystalline silicon on said 0 0 substrate to a thickness in the range of 100A to 750A; and forming said gate electrode and input/output terminals subsequent to formation of said polycrystalline silicon film.
Claim 19
Dependent Claim
92 words
A process for fablicating a field effect transistor having a semiconductor substrate, a thin polycrystalline silicon film formed on said substrate, a gate electrode formed on said polycrystalline silicon film over an insulating layer, and input/output terminals connected to a source region and a drain region formed in said polycrystalline silicon film, said process comprising the steps of: depositing polycrystalline silicon on said 0 0 substrate to a thickness in the range of 100A to 750A; and forming said gate electrode and input/output terminals subsequent to formation of said polycrystalline silicon film.
Claim 20
Dependent Claim
50 words
The process as set forth in claim 16, wherein said step of depositing said polycrystalline silicon film is performed by forming a film at a thickness greater than desired of the finished transistor and then exposing the film to thermal oxidation until the film is reduced to the desired thickness.
Claim 21
Dependent Claim
22 words
The process as set forth in claim 16, wherein 0 0 the range of thickness of said film is 100A to 600A.
Claim 22
Dependent Claim
20 words
The process as set forth in claim 18, wherein the range of thickness of said layer is 200A to 500A.
Claim 23
Dependent Claim
58 words
An IC chip comprising: a semiconductor substrate; an insulating layer formed on said substrate; a polycrystalline silicon layer formed over said substrate and said insulating layer; a first semiconductor device of a first conductivity type formed on said polycrystalline silicon layer; and a second semiconductor device of a second, opposing conductivity type formed on said polycrystalline silicon layer.
Claim 24
Dependent Claim
58 words
An IC chip comprising: a semiconductor substrate; an insulating layer formed on said substrate; a polycrystalline silicon layer formed over said substrate and said insulating layer; a first semiconductor device of a first conductivity type formed on said polycrystalline silicon layer; and a second semiconductor device of a second, opposing conductivity type formed on said polycrystalline silicon layer.
Claim 25
Dependent Claim
31 words
The IC chip as set forth in claim 20, wherein said first and second semiconductor devices are MOS transistor having respective source regions and drain regions in said polycrystalline silicon layer.
Claim 26
Dependent Claim
27 words
The IC chip as set forth in claim 21, wherein said source region of said first semiconductor device abuts said drain region of said second semiconductor device.
Claim 27
Dependent Claim
84 words
The IC chip as set forth in claim 22, which is produced by a process comprising the steps of: forming an insulating layer deposited on a semiconducting substrate, the insulating layer leaving a section of said semiconductor substrate exposed; depositing a polycrystalline silicon layer over said insulating layer and said exposed section; forming MOS transistors on said polycrystalline silicon layer over said insulating layer and over said exposed section; and forming input/output terminals and connecting electrodes which connects said MOS transistors to each other.
Claim 28
Dependent Claim
45 words
The IC chip as set forth in claim 23, in which additional steps of performing ion implantation of the same elemental family as silicon into said polycrystalline silicon layer and of annealing said polycrystalline silicon layer follow said step of depositing said polycrystalline silicon layer.
Claim 29
Dependent Claim
20 words
The IC chip as set forth in claim 23, wherein said MOS transistors are formed in a common process step.
Claim 30
Dependent Claim
23 words
The IC chip as set forth in claim 25, wherein formation of said input/output terminals and connecting electrodes includes a single photo-lithographic step.
Claim 31
Dependent Claim
26 words
The IC chip as set forth in claim 26, wherein said polycrystalline silicon layer has a thickness in 0 0 the range of 100A to 750A.
Claim 32
Dependent Claim
23 words
The IC chip as set forth in claim 27, wherein 0 0 the range of thickness of said layer is 100A to 600A.
Claim 33
Dependent Claim
22 words
The IC chip as set forth in claim 28, wherein 0 the range of thickness of said layer is 200A to 500A.
Claim 34
Dependent Claim
86 words
A process for producing an IC chip including MOS transistors, comprising the steps of: forming an insulating layer over a semiconducting substrate, said insulating layer leaving a section of said semiconductor substrate exposed; depositing a polycrystalline silicon layer over said insulating layer and said exposed section; forming MOS transistors on said polycrystalline silicon layer over said insulating layer and said exposed section; and forming input/output terminals providing external connections to and from the MOS transistors and connecting electrodes which connect said MOS transistors to each other.
Claim 35
Dependent Claim
86 words
A process for producing an IC chip including MOS transistors, comprising the steps of: forming an insulating layer over a semiconducting substrate, said insulating layer leaving a section of said semiconductor substrate exposed; depositing a polycrystalline silicon layer over said insulating layer and said exposed section; forming MOS transistors on said polycrystalline silicon layer over said insulating layer and said exposed section; and forming input/output terminals providing external connections to and from the MOS transistors and connecting electrodes which connect said MOS transistors to each other.
Claim 36
Dependent Claim
44 words
The process as set forth in claim 30, in which steps of performing ion implantation of the same elemental family as silicon into said polycrystalline silicon layer and of annealing said polycrystalline ' silicon layer follow said step of depositing said polycrystalline silicon layer.
Claim 37
Dependent Claim
19 words
The process as set forth in claim 30, wherein said MOS transistors are formed in a common process step.
Claim 38
Dependent Claim
25 words
The process as set forth in claim 32, wherein said input/output gates and connecting electordes are formed with the aid of a single photo-lithographic step.
Claim 39
Dependent Claim
24 words
The process as set forth in claim 30, wherein said polycrystalline silicon layer has a thickness in 0 the range of 100A to 750A.
Claim 40
Dependent Claim
22 words
The process as set forth in claim 34, wherein 0 0 the range of thickness of said layer is 100A to 600A.
Claim 41
Dependent Claim
21 words
The process as set forth in claim 36, wherein 0 the range of thickness of said layer is 200A to 500A.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.