Patent EP0272232A2 successfully refreshed from Google Patents.
Patent US2015656A successfully refreshed from Google Patents.
Patent EP0150811A2 successfully refreshed from Google Patents.
EP0150811A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and apparatus for recording digital signals
Assignee: Hitachi Ltd
•
Filing: 1985-01-24
•
Granted: —
•
Expires: 2005-01-24
Abstract
Abstract Disclosed is a method of the arrangement of the error detection/correction code appended to the recording signal for a PCM recorder, that ensures detection and/or correction of a dropout or error of the information block address in the playback operation. In recording digital signals on a recording medium, the recording signal (8) is formatted in n-word blocks, each block including a sync signal (4) for providing a reference timing for the playback operation, control signal (5) releated to the digital signal, block address signal (6) for identifying the order of n words, error detection signal (7) for detecting the error in the control signal and block address signal, and error detection/correction code (9) used for the error detection and/or correction for the n-word block. The recording system includes an error detection/correction code generating circuit (17) which produces error detection/correction codes using a Reed Solomon code or b-adjacent code. The generated error detection/correction codes are collected through a multiplexer (18) so that a recording signal is arranged, and it is recorded on the recording medium.
Inventors
- 👤 Hiroo Okamoto
- 👤 Masaharu Kobayashi
- 👤 Takaharu Noguchi
- 👤 Takao Arai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 20:36
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
128 words
A method of recording digital signals wherein said digital signals are partitioned into blocks each consisting of digital signals (8) of n in number (n is a positive integer) that are added by a synchronizing signal (4) providing a reference timing for the playback operation, a control signal (5) related to said digital signals, an identification signal (6) for recognizing the order of said n digital signals, an error detection code (7) for detecting at least an error in said control signal and identification signal, and an error detection and correction code (9) for detecting and/or correcting at least an error in said n digital signal, characterized in that said error detection and correction code (9) is produced from said identification signal (6) and n digital signals (8).
Claim 2
Independent Claim
128 words
A method of recording digital signals wherein said digital signals are partitioned into blocks each consisting of digital signals (8) of n in number (n is a positive integer) that are added by a synchronizing signal (4) providing a reference timing for the playback operation, a control signal (5) related to said digital signals, an identification signal (6) for recognizing the order of said n digital signals, an error detection code (7) for detecting at least an error in said control signal and identification signal, and an error detection and correction code (9) for detecting and/or correcting at least an error in said n digital signal, characterized in that said error detection and correction code (9) is produced from said identification signal (6) and n digital signals (8).
Claim 3
Dependent Claim
48 words
A digital signal recording method according to claim 1, wherein said error detection code is obtained through the modulo-2 addition for said control signal and said identification signal, and wherein said error detection and correction code for said n digital signals comprises a Reed-Solomon code or b-adjacent code.
Claim 4
Independent Claim
171 words
A method of processing digital signals to be recorded comprises the steps of: (a) partitioning said digital signals into blocks of n data words (8) (n is a positive integer), and appending at the top of each block a synchronizing signal (4) for providing a reference timing for the playback operation, a control signal (5) related to conversion parameters of said digital signals, and a block address signal (6) for identifying the order of said n data words; (b) extracting an error detection parity word (7) from said control signal and said block address signal, and arranging said parity word successively to said block address signal; and (c) extracting error detection and correction code words (9) for detecting and/or correcting at least an error word in said data words from said block address signal and said n data words, and appending said code word to said n data words, whereby the error detection word for the block address signal of each block is duplexed without increasing the number of detection words.
Claim 5
Independent Claim
171 words
A method of processing digital signals to be recorded comprises the steps of: (a) partitioning said digital signals into blocks of n data words (8) (n is a positive integer), and appending at the top of each block a synchronizing signal (4) for providing a reference timing for the playback operation, a control signal (5) related to conversion parameters of said digital signals, and a block address signal (6) for identifying the order of said n data words; (b) extracting an error detection parity word (7) from said control signal and said block address signal, and arranging said parity word successively to said block address signal; and (c) extracting error detection and correction code words (9) for detecting and/or correcting at least an error word in said data words from said block address signal and said n data words, and appending said code word to said n data words, whereby the error detection word for the block address signal of each block is duplexed without increasing the number of detection words.
Claim 6
Dependent Claim
22 words
A digital signal processing method according to claim 3, wherein said data blocks are recorded sequentially on separate tracks or same tracks.
Claim 7
Independent Claim
249 words
An apparatus for recording digital signals comprising: (a) a random access memory (RAM) (13) in which input digital signals are stored divisionally in units of data word; (b) address control means (14) which controls the read and write operations of said RAM, and generates a block address for identifying words in a block including a specifi - ed number of units of data word in response to the reading of said RAM; (c) synchronizing signal generating means (11) for generating a synchronizing signal which is appended at the top of each block signal for providing a reference timing for the playback operation; (d) control parameter generating means (12) for generating a control signal related to conversion parameters in said analog-to-digital conversion; (e) error detection word generating means (15) for producing an error detection parity word based on a block address provided by said address control means and a control signal provided by said control parameter generating means; (f) error detection and correction word generating means (17) for producing an error detection and correction word used to detect and/or correct errors in a data word and block address basing on a data word provided by said RAM and a block address provided by said address control means; and (g) multiplexer means (18) for sequentially selecting outputs of said synchronizing signal generating means, control parameter generating means, address control means, error detection word generating means, RAM, and error detection and correction word generating means, so as to arrange a data block.
Claim 8
Independent Claim
249 words
An apparatus for recording digital signals comprising: (a) a random access memory (RAM) (13) in which input digital signals are stored divisionally in units of data word; (b) address control means (14) which controls the read and write operations of said RAM, and generates a block address for identifying words in a block including a specifi - ed number of units of data word in response to the reading of said RAM; (c) synchronizing signal generating means (11) for generating a synchronizing signal which is appended at the top of each block signal for providing a reference timing for the playback operation; (d) control parameter generating means (12) for generating a control signal related to conversion parameters in said analog-to-digital conversion; (e) error detection word generating means (15) for producing an error detection parity word based on a block address provided by said address control means and a control signal provided by said control parameter generating means; (f) error detection and correction word generating means (17) for producing an error detection and correction word used to detect and/or correct errors in a data word and block address basing on a data word provided by said RAM and a block address provided by said address control means; and (g) multiplexer means (18) for sequentially selecting outputs of said synchronizing signal generating means, control parameter generating means, address control means, error detection word generating means, RAM, and error detection and correction word generating means, so as to arrange a data block.
Claim 9
Dependent Claim
36 words
A digital signal recording apparatus according to claim 5 comprising means (19, 20) including a modulation means and a recording head for recording signals of data block provided by said multiplexer means onto a recording medium.
Claim 10
Dependent Claim
28 words
A digital signal recording apparatus according to claim 6, wherein said recording medium comprises a magnetic tape, and said recording head comprises a multi-track head or rotary head.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.