Patent EP0150084A2 successfully refreshed from Google Patents.
EP0150084A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Architecture for intelligent control of data communication adapters
Assignee: Texas Instruments Inc
•
Filing: 1985-01-02
•
Granted: —
•
Expires: 2005-01-02
Abstract
Abstract A communications system of the token-passing, closed- loop type for use as a local area network employs an adapter (10) at each station for coupling a host processor (12) to a one-way signal path (11). The host processor (12) includes a host CPU (31), main memory (32), and a system bus (33, 34). To transmit a message from one station to another, a frame of data is created in the main memory (32) by the host CPU). The adapter (10) is coupled to the main memory by the system bus, and includes a local CPU (21), a local read/write memory (22), and a local bus (24). The message frame to be transmitted is copied into the local readiwrite memory by way of the system bus (34) and local bus (24), when initiated by the host CPU (31). A transmit and receive controller (16) is coupled to the local bus (24) to directly access the local read/write memory (22). When this station has access to the loop, i.e., receives a free token, the transmit and receive controller (16) copies the message frame from the local read/write memory (22) to the outgoing signal path (11), converting from parallel to serial. When the transmit and receive controller (16) receives a message addressed to this station, it converts it from serial to parallel, and copies the message frame into the local read/write memory (22) via the
Inventors
- 👤 Michael W. Patrick
- 👤 George Buchanan
- 👤 David S. Laffitte
- 👤 Brian Shore
- 👤 Donald M. Walters Jr.
- 👤 Carrell R. Killebrew Jr.
- 👤 Otto N. Fanini
- 👤 Ki Suk Chang
- 👤 Stephen P. Sacarisen
- 👤 Mark A. Stambaugh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 23:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/128; G06F13/14; G06F13/36; G06F13/362; G06F13/38; G06F13/382; G06F13/385; H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/427; H04L12/433
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
253 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: f) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having system bus means Interconnecting said CPU, main memory, and peripheral I/O devices; ii) a communications processor containing a local CPU, a read-only memory, and a local read/write memory; said communications processor having local bus means interconnecting said local CPU, read-only memory, and local read/write memory; iii) first access means connecting said system bus to said local bus means whereby said main CPU can transfer data to said local read/write memory and said local CPU can transfer data to said main memory, iv) receiving means having an input coupled to said signal path and an output coupled to a receive buffer memory and transmitting means having an output coupled to said signal path and an input coupled to a transmit buffer memory v) transmit/receive control means responsive to receipt of data from said signal path in said receiving means, vi) second access means connecting said receive buffer memory and said transmit buffer memory to said local bus means, and responsive to said transmfit/receive control means to access said local read/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the buffer memory.
Claim 2
Dependent Claim
253 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: f) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having system bus means Interconnecting said CPU, main memory, and peripheral I/O devices; ii) a communications processor containing a local CPU, a read-only memory, and a local read/write memory; said communications processor having local bus means interconnecting said local CPU, read-only memory, and local read/write memory; iii) first access means connecting said system bus to said local bus means whereby said main CPU can transfer data to said local read/write memory and said local CPU can transfer data to said main memory, iv) receiving means having an input coupled to said signal path and an output coupled to a receive buffer memory and transmitting means having an output coupled to said signal path and an input coupled to a transmit buffer memory v) transmit/receive control means responsive to receipt of data from said signal path in said receiving means, vi) second access means connecting said receive buffer memory and said transmit buffer memory to said local bus means, and responsive to said transmfit/receive control means to access said local read/write memory for writing received data from the receive buffer memory to the local read/write memory and reading transmit data from the local read/write memory to the buffer memory.
Claim 3
Dependent Claim
237 words
A system according to claim 1 wherein: said signal path is a closed, one-way path, and each station receives data from an upstream direction in the path and transmits data to a downstream direction in the path, said access to said signal path is controlled by a token included in the transmitted data and passed from station to station around the closed path, data is transmitted on said signal path in bit-serial format, said receiving means includes serial-to-parallel conversion means, said transmitting means includes parallel-to-serial conversion means, a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred by said first access means upon initiation by said main CPU via said system bus and said local bus into said local and said local read/write memory, and subsequently such frame is transferred under control of said transmit/receive control means via said local bus and said transmit buffer memory to said transmitting means, said frames of data created in said main memory and transmitted on said signal path by said stations include a destination address identifying a particular one of the stations, and a source address identifying the originating station, and said local CPU executes instructions fetched from a local ROM via said local bus means, and said main CPU executes instructions fetched from said main memory via said memory bus.
Claim 4
Dependent Claim
160 words
A digital system comprising: a) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; b) a local processor containing a local CPU, and a local read/write memory; said local processor having a local bidirectional address/data bus interconnecting said local CPU and local read/write memory; c) first direct memory access means connecting said system bus to said local bus whereby said main CPU can initiate access to said local read/write memory and said local CPU can initiate access to said main memory, each said direct address being under control of said first direct memory access means, d) second direct memory access means connected to said local bus means to directly access said local read/write memory for writing received data from a remote data path to said local read/write memory and reading data from the local read/write memory to said remote data path.
Claim 5
Dependent Claim
160 words
A digital system comprising: a) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; b) a local processor containing a local CPU, and a local read/write memory; said local processor having a local bidirectional address/data bus interconnecting said local CPU and local read/write memory; c) first direct memory access means connecting said system bus to said local bus whereby said main CPU can initiate access to said local read/write memory and said local CPU can initiate access to said main memory, each said direct address being under control of said first direct memory access means, d) second direct memory access means connected to said local bus means to directly access said local read/write memory for writing received data from a remote data path to said local read/write memory and reading data from the local read/write memory to said remote data path.
Claim 6
Dependent Claim
144 words
A system according to claim 3 including bus arbitration means coupled to said local bus and receiving bus request signals individually from said first access means, said second access means, and said local CPU; said bus arbitration means granting access to said local bus in the order of priority of (1) said second access means, (2) said first access means, and (3) said local CPU, said local CPU executes instructions fetched from a local ROM via said local bus, and said main CPU executes instructions fetched from said main memory via said system bus, the first access means includes memory-mapped I/O means by which the main CPU accesses control register means in the first access means, and wherein direct memory access of the local read/write memory from the system bus is initiated by said control register means when written into by the main CPU.
Claim 7
Dependent Claim
126 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, and a system bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, and a local bus connecting the local CPU and local memory; b) a system interface device coupling said local bus to said system bus for transferring data between said system memory and said local memory; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said tocat memory; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local bus.
Claim 8
Dependent Claim
126 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, and a system bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, and a local bus connecting the local CPU and local memory; b) a system interface device coupling said local bus to said system bus for transferring data between said system memory and said local memory; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said tocat memory; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local bus.
Claim 9
Dependent Claim
180 words
An adapter according to claim 5 wherein: said local read-only memory is contained within said data communications Interface device, said system interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU, said data communications interface device includes a direct memory access channel by which data is transferred between said signal path and said local memory under control of the data communication interface device after initiation of the transfer by the local CPU or the data communications interface device. said programmable processor device includes bus arbitration means to control access to said local bus, and said data communications interface device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
Claim 10
Dependent Claim
168 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, and a system bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, and a local multiplexed address/data bus connecting the local CPU and local memory; said local memory including read-only memory for storing program instructions executed by said local CPU and Including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system bus for transferring message data between said system memory and said local memory by direct memory access in both directions; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said local memory by;direct memory access in both directions; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 11
Dependent Claim
168 words
A data communications adapter connecting a processor system to a data communications signal path; said processor system having a system CPU, a system memory, and a system bus; said adapter comprising: a) a programmable processor device having a local CPU, a local memory, and a local multiplexed address/data bus connecting the local CPU and local memory; said local memory including read-only memory for storing program instructions executed by said local CPU and Including read/write memory for temporarily storing message data; b) a system interface device coupling said local address/data bus to said system bus for transferring message data between said system memory and said local memory by direct memory access in both directions; c) a data communications interface device coupling said local bus to said signal path for transferring data between said signal path and said local memory by;direct memory access in both directions; d) wherein said data communications interface device, said system interface device, and said local CPU all contend for control of said local address/data bus.
Claim 12
Dependent Claim
164 words
An adapter according to claim 7 wherein said system interface device contains a memory-mapped I/O channel by which said system CPU accesses said local memory to transfer command and status information, and contains a direct memory access channel by which data is transferred between the system memory and the local memory under control of the system interface device after initiation of the transfer by the system CPU or the local CPU; wherein said data communications interface device includes a direct memory access channel by which data is transferred between said signal path and said local memory under control of the data transfer by the local CPU or the data communications interface device; and wherein said programmable processor device includes bus arbitration means to control access to said local bus, and said data communications interface device has highest priority of such access, said system interface device has the next higher priority of such access, and said local CPU has the lower priority of such access.
Claim 13
Dependent Claim
234 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; ii) a single-chip microprocessor device containing a local CPU, a local read/write memory a local address/data bus means interconnecting said local CPU and local read/write memory, a timer having at least one count register accessed by said local bus means, and a bus arbiter coupled to and controlling access to said local bus; iii) coupling means connecting said system bus to said local bus means whereby said main CPU can access said local read/write memory and said local CPU can access said main memory, iv) receiving means having an input coupled to said signal path and an output coupled to said local bus means, and transmitting means having an output coupled to said signal path and an input coupled to said local bus means, v) transmit/receive control means responsive to receipt of data from said signal path in said receiving means to directly access said local read/write memory for writing received data to the local read/write memory and reading transmit data from the local read/write memory.
Claim 14
Dependent Claim
234 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected to said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; ii) a single-chip microprocessor device containing a local CPU, a local read/write memory a local address/data bus means interconnecting said local CPU and local read/write memory, a timer having at least one count register accessed by said local bus means, and a bus arbiter coupled to and controlling access to said local bus; iii) coupling means connecting said system bus to said local bus means whereby said main CPU can access said local read/write memory and said local CPU can access said main memory, iv) receiving means having an input coupled to said signal path and an output coupled to said local bus means, and transmitting means having an output coupled to said signal path and an input coupled to said local bus means, v) transmit/receive control means responsive to receipt of data from said signal path in said receiving means to directly access said local read/write memory for writing received data to the local read/write memory and reading transmit data from the local read/write memory.
Claim 15
Dependent Claim
263 words
A system according to claim 9 wherein: said signal path is a closed, one-way path, and each station receives data from an upstream direction in the path and transmits data to a downstream direction in the path, said access to said signal path is controlled by a token included in the transmitted data and passed from station to station around the closed path, data is transmitted on said signal path in bit-serial format, said receiving means includes serial-to-parallel conversion means, said transmitting means includes parallel-to-serial conversion means, and wherein said local address/data bus means and said system bus are parallel busses, ,a frame of a plurality of bytes of data to be transmitted is created in said memory under control of said main CPU, and such frame is transferred upon Initiation by said main CPU via said system bus and said local bus means into said local read/write memory, and subsequently such frame is transferred under control of said transmit/receive control means via said local bus to said transmitting means, said frames of data created in said main memory and transmitted on said signal path by said stations include a destination address identifying a particular one of the stations, and a source address identifying the originating station, said local CPU executes instructions fetched from a local ROM via said local bus means as controlled by said bus arbiter, and said main CPU executes instructions fetched from said main memory via said system bus, said timer interrupts execution of said instructions in said local CPU after a timer period determined by said count register.
Claim 16
Dependent Claim
303 words
A digital data communications system comprising: a) a closed, one-way, bit-serial signal path, b) a plurality of independent stations connected in said signal path, each station receiving digital data including an access-control token from the path and transmitting digital data including an access-control token to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; ii) a single-chip microprocessor device containing a local CPU, a local read/write memory, a timer having count register means and having means to interrupt said logal CPU, local address/data bus means interconnecting said local CPU local read/write memory and count register of the timer, and bus arbiter means controlling access to said local bus means; ili) first access control means including said bus arbiter means and connecting said system bus to said local bus means whereby said main CPU initiates direct access to said local read/write memory via said system bus and said local bus means, and said local CPU initiates access to said main memory, iv) receiving means having a serial input coupled to said signal path and a parallel output coupled to said local address/data bus means, and transmitting means having s serial output coupled to said signal path and a parallel input coupled to said local address/data bus means, v) second access means including said bus arbiter means and connecting said output of said transmit timing means to said local bus means, and responsive to said transmit/receive control means to initiate access to said local read/write memory via said local bus means for writing data received from the signal path to the local read/write memory and reading transmit data from the local read/write memory for coupling to the signal path.
Claim 17
Dependent Claim
303 words
A digital data communications system comprising: a) a closed, one-way, bit-serial signal path, b) a plurality of independent stations connected in said signal path, each station receiving digital data including an access-control token from the path and transmitting digital data including an access-control token to said path, each said station comprising: i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; ii) a single-chip microprocessor device containing a local CPU, a local read/write memory, a timer having count register means and having means to interrupt said logal CPU, local address/data bus means interconnecting said local CPU local read/write memory and count register of the timer, and bus arbiter means controlling access to said local bus means; ili) first access control means including said bus arbiter means and connecting said system bus to said local bus means whereby said main CPU initiates direct access to said local read/write memory via said system bus and said local bus means, and said local CPU initiates access to said main memory, iv) receiving means having a serial input coupled to said signal path and a parallel output coupled to said local address/data bus means, and transmitting means having s serial output coupled to said signal path and a parallel input coupled to said local address/data bus means, v) second access means including said bus arbiter means and connecting said output of said transmit timing means to said local bus means, and responsive to said transmit/receive control means to initiate access to said local read/write memory via said local bus means for writing data received from the signal path to the local read/write memory and reading transmit data from the local read/write memory for coupling to the signal path.
Claim 18
Dependent Claim
190 words
A system according to claim 11 wherein: said receiving means includes serial-to-parallel conversion means, said transmitting means includes parallel-to-serial conversion means, and wherein each of said local address/data bus means and system bus includes a parallel bus, a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred upon initiation by said main CPU and control by said first access means via said system bus and said local bus means into said local read/write memory, and subsequently such frame is transferred under control of said second access means via said local bus means to aid transmitting means, said local CPU executes instructions fetched from a local read-only memory extended to said microprocessor device via said local bus means, and said main CPU executes instructions fetched from said main memory via said system bus, said local bus means is a bidirectional, multiplexed address/data bus, and said bus arbiter means controls access to said local bus means for an outgoing address and an incoming instruction for said fetch of instructions for said local CPU.
Claim 19
Dependent Claim
253 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected in said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: 1) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; ii) a single-chip microprocessor device containing a local CPU, local address/data bus means, a timer having a count register, a clocked decrement input for said count register, a latch register means for Interrupting said local CPU when said count register decrements to zero, and means for loading said count register from said latch register when said count register decrements to zero, iii) a local read/write memory coupled to said local bus means, iv) coupling means connecting said system bus to said local bus means whereby said main CPU can access said local read/write memory and said local CPU can access said main memory, v) receiving means having an input coupled to said signal path and an output coupled to said local bus means, and transmitting means having an output coupled to said signal path and an input coupled to said local bus means, vi) transmit/receive control means responsive to receipt of data from said signal path In said receiving means to directly access said local read/write memory for writing received data to the local read/write memory and reading transmit data from the local read/write memory.
Claim 20
Dependent Claim
253 words
A digital data communications system comprising: a) a signal path, b) a plurality of stations connected in said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: 1) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; ii) a single-chip microprocessor device containing a local CPU, local address/data bus means, a timer having a count register, a clocked decrement input for said count register, a latch register means for Interrupting said local CPU when said count register decrements to zero, and means for loading said count register from said latch register when said count register decrements to zero, iii) a local read/write memory coupled to said local bus means, iv) coupling means connecting said system bus to said local bus means whereby said main CPU can access said local read/write memory and said local CPU can access said main memory, v) receiving means having an input coupled to said signal path and an output coupled to said local bus means, and transmitting means having an output coupled to said signal path and an input coupled to said local bus means, vi) transmit/receive control means responsive to receipt of data from said signal path In said receiving means to directly access said local read/write memory for writing received data to the local read/write memory and reading transmit data from the local read/write memory.
Claim 21
Dependent Claim
208 words
A system according to claim 13 wherein: said signal path is a closed, one-way path, and each station receives data from an upstream direction in the path and transmits data to a downstream direction in the path, said access to said signal path is controlled by a token included in the transmitted data and passed from station to station around the closed path, data is transmitted on said signal path in bit-serial format, said receiving means includes serial-to-parallel conversion means, said transmitting means includes parallel-to-serial conversion means, and wherein said local address/data bus means and said system bus are parallel busses, a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred upon initiation by said main CPU via said system bus and said local bus means into said local read/write memory, and subsequently such frame is transferred under control of said transmit/receive control means via said local bus to said transmitting means, said frames of data created in said main memory and transmitted on said signal path by said stations include a destination address identifying a particular one of the stations, and a source address identifying the origination station.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.