Patent US215562A successfully refreshed from Google Patents.
Patent EP0149401A2 successfully refreshed from Google Patents.
EP0149401A2
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EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-12-28
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Granted: —
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Expires: 2004-12-28
Abstract
Abstract A semiconductor memory device in which a bipolar memory cell includes two cross-coupled transistors. The collector load is a Schottky barrier diode (SBDIa). A capacitor (C P11 , C P12 ) is formed to be connected to the Schottky barrier diode. The capacitor is formed by a junction between a p + -type diffusion region (10a) and an N + -type buried layer (2) functioning as a collector of the transistor. The p + -type diffusion region (10a) is formed in the periphery of the Schottky barrier diode and between a metal layer (13) connected to a word line and the N + -type buried layer (2). By the capacitor, the stability of the memory holding state is improved without deteriorating the operating speed of the memory cell.
Inventors
- 👤 Yasuhisa Sugo
- 👤 Tohru Takeshima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 19:49
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/10; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; H10D; H10D8/00; H10D8/60; H10D84/00; H10D84/60; H10D84/611; H10D84/613
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
226 words
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines intersecting to said word lines; bipolar memory cells arranged on intersecting portions between said word lines and said bit lines; each of said bipolar memory cells comprising a first transistor, a second transistor, and a load connected between the collector of each of said first transistor and said second transistor and one of said word lines; the base and the collector of said first transistor being respectively connected to the collector and the base of said second transistor; said load comprising a Schottky barrier diode and a load resistor connected in parallel; said load further comprising a capacitor connected in parallel with said Schottky barrier diode; each of said first transistor and said second transistor comprising a semiconductor layer having a first conductivity type and operatively functioning as a collector region; and a high concentration buried layer formed in said semiconductor layer and having said first conductivity type; said Schottky barrier diode comprising a Schottky barrier region formed at the surface of said semiconductor layer; in said Schottky barrier region, a semiconductor region having a second conductivity type being formed so as to reach said high concentration buried layer; said capacitor being formed by a junction between said semiconductor region and said high c on c en - tration buried layer.
Claim 2
Dependent Claim
226 words
A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines intersecting to said word lines; bipolar memory cells arranged on intersecting portions between said word lines and said bit lines; each of said bipolar memory cells comprising a first transistor, a second transistor, and a load connected between the collector of each of said first transistor and said second transistor and one of said word lines; the base and the collector of said first transistor being respectively connected to the collector and the base of said second transistor; said load comprising a Schottky barrier diode and a load resistor connected in parallel; said load further comprising a capacitor connected in parallel with said Schottky barrier diode; each of said first transistor and said second transistor comprising a semiconductor layer having a first conductivity type and operatively functioning as a collector region; and a high concentration buried layer formed in said semiconductor layer and having said first conductivity type; said Schottky barrier diode comprising a Schottky barrier region formed at the surface of said semiconductor layer; in said Schottky barrier region, a semiconductor region having a second conductivity type being formed so as to reach said high concentration buried layer; said capacitor being formed by a junction between said semiconductor region and said high c on c en - tration buried layer.
Claim 3
Dependent Claim
25 words
A semiconductor memory device as set forth in claim 1, wherein said semiconductor region is formed in the entire periphery of said Schottky barrier region.
Claim 4
Dependent Claim
27 words
A semiconductor memory device as set forth in claim 1, wherein said semiconductor region is formed in a part of said periphery of said Schottky barrier region.
Claim 5
Dependent Claim
18 words
A semiconductor memory device as set forth in claim 1, wherein said semiconductor region is a diffusion region.
Claim 6
Dependent Claim
34 words
A semiconductor memory device as set forth in claim 1, wherein said semiconductor region is formed between a metal layer connected to said one of said word lines and said high concentration buried layer.
Claim 7
Dependent Claim
46 words
A semiconductor memory device as set forth in claim 1, wherein each of said first transistor and said second transistor is a multiemitter NPN transistor having a first emitter connected to a hold current line and a second emitter connected to one of said bit lines.
Claim 8
Dependent Claim
28 words
A semiconductor memory device as set forth in claim 6, wherein said first conductivity type is an N-type conductivity and said second conductivity type is a P-type conductivity.
Claim 9
Dependent Claim
49 words
A semiconductor memory device as set forth in claim 7, wherein a guard ring is formed on the periphery of said Schottky barrier region, said guard ring being formed by a P +- type diffusion region, said semiconductor region being formed in least a part of said guard ring.
References Cited (Backward Citations)
No citation records indexed.
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