Patent EP0149392A2 successfully refreshed from Google Patents.
EP0149392A2
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EP
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Digital computer system
Assignee: Fujitsu Ltd
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Filing: 1984-12-20
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Granted: —
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Expires: 2004-12-20
Abstract
Abstract A digital computer system including a central processing unit CPU (1) ; a main storage unit MSU (4) ; a buffer storage unit (5) functioning as an effective memory device for the CPU with a high speed access time ; and a store buffer device (2) receiving data identical to that to be stored in the buffer storage unit and control information for the received data in response to requests from the CPU and transferring the received data in response and control information to the MSU. The transmission operation from the CPU to the store buffer device and from the store buffer device to the MSU are effected on the basis of a machine cycle timing. The store buffer device (2) includes a controller (29), a plurality of data register sets (21, 22) including data registers for receiving data to be stored in the MSU, a byte mark register set (23) for receiving information indicating storable data in the data registers, and an address register set (24) for receiving a starting store addresss in the MSU for the data to be stored in the data registers.
Inventors
- 👤 Tetsuya Morioka
- 👤 Tsutomu Tanaka
- 👤 Katsumi Onishi
- 👤 Yuji Oinaga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 15:58
CPC Classifications
G; G06; G06F; G06F15/00; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F13/00; G06F13/14; G06F13/16
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
234 words
A digital computer system comprising: a central processing unit; a main storage unit having a large amount of memory capacity; a buffer storage unit provided between the central processing unit and the main storage unit and functioning as an effective memory device for the central processing unit with a high speed access time; and a store buffer device provided between the central processing unit and the main storage unit, receiving data identical to that to be stored in the buffer storage unit and control information for the received data in response to requests from the central processing unit and transferring the received data and control information to the main storage unit; said transmission operation from the central processing unit to the store buffer device and transfer operation from the store buffer device to the main storage unit being effected on the basis of a machine cycle timing, wherein said store buffer device includes a controller, a plurality of data register sets, each set including a plurality of data registers for receiving data to be stored in the main storage unit, a byte mark register set forming a plurality of byte mark registers for receiving information indicating storable data in the data registers, and an address register set forming a plurality of address registers for receiving a starting store address in the main storage unit for the data to be stored in the data registers.
Claim 2
Dependent Claim
234 words
A digital computer system comprising: a central processing unit; a main storage unit having a large amount of memory capacity; a buffer storage unit provided between the central processing unit and the main storage unit and functioning as an effective memory device for the central processing unit with a high speed access time; and a store buffer device provided between the central processing unit and the main storage unit, receiving data identical to that to be stored in the buffer storage unit and control information for the received data in response to requests from the central processing unit and transferring the received data and control information to the main storage unit; said transmission operation from the central processing unit to the store buffer device and transfer operation from the store buffer device to the main storage unit being effected on the basis of a machine cycle timing, wherein said store buffer device includes a controller, a plurality of data register sets, each set including a plurality of data registers for receiving data to be stored in the main storage unit, a byte mark register set forming a plurality of byte mark registers for receiving information indicating storable data in the data registers, and an address register set forming a plurality of address registers for receiving a starting store address in the main storage unit for the data to be stored in the data registers.
Claim 3
Dependent Claim
51 words
A digital computer system according to claim 1, wherein the number of data registers in each data register set is identical, the corresponding data registers in the data register sets being functionally connectable in series to perform first-in and first-out queuing in response to the length of data to be stored.
Claim 4
Dependent Claim
23 words
A digital computer system according to claim 2, wherein each data register in the data register sets has the same number of bits.
Claim 5
Dependent Claim
79 words
A digital computer system according to claim 3, wherein the store buffer device further includes a plurality of data buffer registers arranged at a preceding portion of the data register sets and being connected to the corresponding data register sets, the desired data buffer register being operatively connected in series to receive the data to be stored and to output the received data to the corresponding data register sets, in response to the length of data to be stored.
Claim 6
Dependent Claim
28 words
A digital computer system according to claim 4, wherein the operatively connecting operation for the data buffer registers can be performed in response to the machine cycle timing.
Claim 7
Dependent Claim
36 words
A digital computer system according to claim 5, wherein series data stored in the functionally connectable data registers is continuously output to the main storage unit in predetermined sets is response to the machine cycle timing.
Claim 8
Dependent Claim
58 words
A digital computer system according to claim 6, wherein the store buffer device further includes a data selection circuit operatively connected to outputs of the respective data register sets, the data selection circuit forming an output path between a desired data register in the desired data register set and a data output terminal(s) to the main storage unit.
Claim 9
Dependent Claim
43 words
A digital computer system according to claim 2, wherein the bit length of each data register is defined by a byte unit, the processing for input and output of the data register being performed on the basis of a plurality of data bytes.
Claim 10
Dependent Claim
15 words
A digital computer system according to claim 2, wherein there are two data register sets.
Claim 11
Dependent Claim
28 words
A digital computer system according to claim 1, wherein each byte mark register has a predetermined number of bits defined by the data length of one data register.
Claim 12
Dependent Claim
33 words
A digital computer system according to claim 2, wherein each byte mark register has a predetermined number of bits corresponding to a sum of the data length of the functionally connectable data registers.
Claim 13
Dependent Claim
97 words
A digital computer system according to claim 1, wherein said store buffer device further includes a byte mark generating circuit connected to the byte mark register set at a preceding portion thereof, the byte mark generating circuit being operable to receive signals of a length of data to be stored and a start address of the data storage and to generate a byte mark signal indicating storable data in the main storage unit for the data stored in the data registers and an actual start storage address in the main storage unit cooperating with the start address.
Claim 14
Dependent Claim
52 words
A digital computer system according to claim 1, wherein the start address signal stored in the address register and the storable data indication signal stored in the byte mark register define an actual start storage address in the main storage unit for the data to be stored, stored in the data registers.
Claim 15
Dependent Claim
63 words
A digital computer system according to claim 1, wherein the number of byte mark registers is identical to the number of the data registers in each data register set, each byte mark register in the byte mark register set corresponding to a data register in each data register set being simultaneously operable with the corresponding data register in the respective data register sets.
Claim 16
Dependent Claim
59 words
A digital computer system according to claim 1, wherein the number of address registers is identical to the number of the data registers in each data register set, each address register in the address register corresponding to a data register in each data register set being simultaneously operable with the corresponding data register in the respective data register sets.
Claim 17
Dependent Claim
58 words
A digital computer system according to claim 14, wherein a series of corresponding registers arranged at one sequence in the data register sets, byte mark register set, and the address register set is independently operable in parallel timing with other series of corresponding registers arranged at other sequences of the register sets to perform input and output operations.
Claim 18
Dependent Claim
57 words
A digital computer system according to claim 15, wherein a series of corresponding registers arranged at one sequence in the data register sets, byte mark register set, and the address register set is independently operable in parallel timing with other series of corresponding registers arranged at other sequences of the register sets to perform-input and output operations.
References Cited (Backward Citations)
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